UCIe 3.0 Is Here: Synopsys IP Solutions Are Ready

By Varun Agrawal

August 6, 2025

Chips have evolved from single, monolithic dies to multi-die designs that integrate several chiplets, each optimized for specific functions such as processing, memory, and data transfer.

With the ecosystem of chiplet providers expanding — and customers wanting the ability to mix-and-match those offerings based on architectural, supply chain, economic, or other variables — the need for fast, reliable, and secure communication between chiplets has never been greater.

That’s exactly what the Universal Chiplet Interconnect Express (UCIe) standard provides. It defines a common interface for die-to-die connectivity, enabling interoperability across vendor solutions and process nodes.

With the recent release of UCIe 3.0, the standard is taking a significant leap forward. It offers double the performance compared to UCIe 2.0, along with improved system-level control and support for new use cases.

As a member of the UCIe Consortium and key contributor to the standard’s development, Synopsys has always been at the forefront of UCIe innovation and adoption. And our complete, silicon-proven IP is ready for the latest iteration of the standard.

Using our UCIe PHY, controller, and verification IP, customers can easily introduce UCIe 3.0 into their designs and accelerate time-to-market.

Why UCIe 3.0 was needed

The original introduction of UCIe was a major milestone for multi-die designs. By establishing a common die-to-die interface, the standard made it possible to integrate chiplets from different vendors and process nodes within a shared package. That foundation directly led to the first wave of chiplet adoption for designs prioritizing modularity and manufacturing flexibility.

As the industry’s adoption of multi-die architectures has grown, expectations for the standard have risen accordingly. Today’s design teams are developing increasingly complex systems that support broader performance ranges, power envelopes, and application requirements. They are integrating more dies per package, targeting advanced workloads, and demanding faster connectivity along with tighter system-level coordination.

The importance of UCIe has grown as a result. Beyond interoperability, UCIe needs to support predictability, efficiency, and scale. As multi-die designs shift from early adoption into production across artificial intelligence (AI), high-performance computing (HPC), and automotive applications, the standard needs to evolve to support those use cases more fully.

UCIe 3.0 is that next step. It was developed to support the trajectory of multi-die designs, and we have made it a priority to support this evolution with silicon-ready IP and EDA flows.

What’s new in UCIe 3.0

UCIe 3.0 introduces significant upgrades that address the bandwidth, latency, and system integration requirements of modern multi-die designs.

The most headline-grabbing change is speed: UCIe 3.0 doubles the maximum data rate from 32 GT/s to 64 GT/s. Data-intensive applications like AI inference, memory and I/O disaggregation, and high-speed accelerator fabrics will immediately recognize a tangible boost in performance. But speed alone doesn’t solve system-level challenges.

To improve power efficiency and reliability at these higher data rates, UCIe 3.0 introduces runtime recalibration, which allows links to adapt to drift and environmental changes during operation. The feature helps guarantee signal integrity without the need for excessive guardbanding.

Another major enhancement is the extended sideband reach — now up to 100 mm — which supports more complex topologies and greater physical separation between chiplets.

Other new features include early firmware download and deterministic priority messaging over sideband channels. Both capabilities help reduce bring-up time and improve system responsiveness during boot and runtime.

Enabling fast UCIe 3.0 adoption

Supporting UCIe 3.0 requires a cohesive set of IP, verification, and design solutions that work together at full speed.

• We have already taped-out our UCIe PHY IP on TSMC and Samsung advanced nodes to target both standard and advanced packaging flows. The PHY is designed for high-speed, low-power operation, with built-in support for runtime recalibration and sideband signaling. When paired with a flexible controller IP supporting PCIe, CXL, and custom streaming protocols, the solution enables engineering teams to align UCIe designs with their specific workloads and system architectures.
• We also offer Verification IP for UCIe that models link behavior, protocol correctness, and system-level interaction, including new features like early firmware loading and deterministic sideband control. These Verification IPs integrate with our emulation and prototyping platforms (ZeBu and HAPS) to validate die-to-die connections well before tapeout.
• Everything ties together in 3DIC Compiler, our unified exploration-to-signoff platform for die/package co-design. It enables teams to design floorplans, routes, and package geometries with UCIe links as a first-class element to manage complexity as performance scales.

Early momentum and what’s next

Even before the official release of UCIe 3.0, we partnered with early adopters to develop designs that deliver higher bandwidth and advanced system coordination. With the new standard now publicly available, this momentum is only increasing.

As the chiplet ecosystem continues to evolve, successful adoption will rely on comprehensive enablement — seamlessly integrating IP, tools, and verification across silicon and system boundaries.

With UCIe 3.0 and Synopsys, that future is already taking shape.

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