Multi-Die Design Challenges: Industry Leaders Provide Insights and Guidance

By Frank Malloy

May 16, 2025

Multi-die designs seamlessly integrate multiple heterogeneous or homogeneous dies in a single package to significantly enhance chip performance and efficiency — making them indispensable for high-performance computing (HPC), artificial intelligence (AI), data analytics, advanced graphics processing, and other demanding applications.

While representing a groundbreaking leap forward, multi-die designs also introduce a host of engineering challenges. Industry leaders from Ansys, Intel, Synopsys, and TSMC participated in a panel discussion at Chiplet Summit 2025, sharing their insights and guidance for how to address these evolving challenges. 

Confronting multi-physics challenges

The transformative benefits of multi-die designs are unquestioned, but the challenges they introduce are daunting. According to the panelists, managing multi-physics interactions — which can impact power and thermal integrity — is particularly difficult.

“There’s a lot of interaction between electrical, mechanical, fluid, and thermal,” said Norman Chang, fellow and chief technologist of the Electronics, Semiconductor, and Optics Business Unit at Ansys.

Design teams need to understand and analyze all of the interactions and impacts of these interconnected domains. “Everything together,” Chang said.

Ever-increasing processing demands further complicate power and thermal management in multi-die designs, said Lalitha Immaneni, VP of architecture, design, and technology solutions and technology development at Intel.

“If you are looking at an AI segment, for instance, where you have increasing bandwidths, the capacity constraints are increasing, power is increasing. In the next five years or 10 years, you are looking at five kilowatts,” she said. “How will we manage that?”

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