Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi-Die Systems
February 15, 2024
Multi-die system design is clearly gaining momentum. Part of this momentum focuses on chiplets and a chiplet ecosystem. A “building block” approach for design will work better if there is a way to get verified, quality building blocks in the form of chiplets. The recent Chiplet Summit became an epicenter for this topic. The conference grew about 2X from last year’s event. Chiplets are a hot topic. IO and memory chiplets are foundational elements for any system and a presentation on this topic by two companies making significant investments in this area caught my eye. Read on to see how Synopsys and Alchip accelerate IO & memory chiplet design for multi-die systems.
Who Presented ?
Related Chiplet
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
- UCIe based 12-bit 12-Gsps Transceiver
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