Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi-Die Systems
February 15, 2024
Multi-die system design is clearly gaining momentum. Part of this momentum focuses on chiplets and a chiplet ecosystem. A “building block” approach for design will work better if there is a way to get verified, quality building blocks in the form of chiplets. The recent Chiplet Summit became an epicenter for this topic. The conference grew about 2X from last year’s event. Chiplets are a hot topic. IO and memory chiplets are foundational elements for any system and a presentation on this topic by two companies making significant investments in this area caught my eye. Read on to see how Synopsys and Alchip accelerate IO & memory chiplet design for multi-die systems.
Who Presented ?
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Blogs
- Faster, More Collaborative SoC and Chiplet Architecture Exploration: Introducing Synopsys Platform Architect Development Kit (PADK)
- Simplifying AI Chip Development: Arm and Synopsys Execs Discuss Chiplet, Subsystem, and IP Integration
- Intel® Shows OCI Optical I/O Chiplet Co-packaged with CPU at OFC2024, Targeting Explosive AI Scaling
- Synopsys and Alchip Collaborate to Streamline the Path to Multi-die Success with Soft Chiplets
Latest Blogs
- 3D-IC Market Outlook: Technology Roadmaps, Readiness, and Design Implications
- Cadence 3D-IC Success Stories: Faster Bandwidth, Lower Power, On-Time Tapeouts
- 3D-IC Test and Reliability: KGD Strategies, Access Architecture, & Failure Mode
- 3D-IC in AI, HPC, and 5G: Bandwidth, Latency, and Energy per Bit Advantages
- Bosch and the chiplet revolution: Enabling software-defined mobility