Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi-Die Systems
February 15, 2024
Multi-die system design is clearly gaining momentum. Part of this momentum focuses on chiplets and a chiplet ecosystem. A “building block” approach for design will work better if there is a way to get verified, quality building blocks in the form of chiplets. The recent Chiplet Summit became an epicenter for this topic. The conference grew about 2X from last year’s event. Chiplets are a hot topic. IO and memory chiplets are foundational elements for any system and a presentation on this topic by two companies making significant investments in this area caught my eye. Read on to see how Synopsys and Alchip accelerate IO & memory chiplet design for multi-die systems.
Who Presented ?
To read the full article, click here
Related Chiplet
- Automotive AI Accelerator
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
Related Blogs
- Synopsys and Alchip Collaborate to Streamline the Path to Multi-die Success with Soft Chiplets
- Intel® Shows OCI Optical I/O Chiplet Co-packaged with CPU at OFC2024, Targeting Explosive AI Scaling
- Alphawave Semi Tapes Out Industry-First, Multi-Protocol I/O Connectivity Chiplet for HPC and AI Infrastructure
- UMI: Extending Chiplet Interconnect Standards To Deal With The Memory Wall
Latest Blogs
- The Growing Importance of Advanced Packaging in Europe – Recap of ERS TechTalk
- Cadence Silicon Success of UCIe IP on Samsung Foundry’s 5nm Automotive Process
- Ayar Labs Optical Connectivity for AI Compute Fabrics
- The APECS Pilot Line: Heterointegration enabling Chiplet Applications
- The Future of Faster, Smaller, and More Efficient Chips: A Breakthrough in Hybrid Bonding