Industry Leaders Discuss “Overcoming the Challenges of Multi-die Systems Verification”
March 18, 2024
Lauro Rizzatti, hardware-assisted verification consultant, served as moderator for a well-attended and lively 2024 DVCon U.S. panel discussion on the challenges in multi-die systems verification.
The hour-long session featured panelists Alex Starr, AMD Corporate Fellow; Bharat Vinta, Director of HW Engineering at Nvidia; Divyang Agrawal, Sr. Director of RISC-V Cores at Tenstorrent; and Arturo Salz, Synopsys Fellow.
What follows is a shortened panel transcript, edited for readability.
Lauro
How is multi-die evolving and growing? More specifically, what advantages have you experienced? Any drawback you can share?
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Blogs
- Streamlining Functional Verification for Multi-Die and Chiplet Designs
- Why 2023 Holds Big Promise for Multi-Die Systems
- Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi-Die Systems
- TSMC Advanced Packaging Overcomes the Complexities of Multi-Die Design
Latest Blogs
- Advancing Europe’s Automotive Chiplet Vision: Arteris Joins CHASSIS to Accelerate Software-Defined Mobility
- 3D-IC Market Outlook: Technology Roadmaps, Readiness, and Design Implications
- Cadence 3D-IC Success Stories: Faster Bandwidth, Lower Power, On-Time Tapeouts
- 3D-IC Test and Reliability: KGD Strategies, Access Architecture, & Failure Mode
- 3D-IC in AI, HPC, and 5G: Bandwidth, Latency, and Energy per Bit Advantages