Industry Leaders Discuss “Overcoming the Challenges of Multi-die Systems Verification”
March 18, 2024
Lauro Rizzatti, hardware-assisted verification consultant, served as moderator for a well-attended and lively 2024 DVCon U.S. panel discussion on the challenges in multi-die systems verification.
The hour-long session featured panelists Alex Starr, AMD Corporate Fellow; Bharat Vinta, Director of HW Engineering at Nvidia; Divyang Agrawal, Sr. Director of RISC-V Cores at Tenstorrent; and Arturo Salz, Synopsys Fellow.
What follows is a shortened panel transcript, edited for readability.
Lauro
How is multi-die evolving and growing? More specifically, what advantages have you experienced? Any drawback you can share?
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Blogs
- Streamlining Functional Verification for Multi-Die and Chiplet Designs
- Why 2023 Holds Big Promise for Multi-Die Systems
- Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi-Die Systems
- TSMC Advanced Packaging Overcomes the Complexities of Multi-Die Design
Latest Blogs
- Blazing the Trail Toward More Scalable, Affordable AI with 3DIMC
- Why Electrical Design Matters in Chiplet Architectures – Part One: Signal Integrity and Power Delivery
- A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution
- Let’s Get Serious: TeraPHY™ Optical Engine Passes the Test for AI Scale-Up at Volume
- Accelerating Early-Stage explorations with Virtual Prototyping for a thriving multi-vendor chiplet ecosystem