Industry Leaders Discuss “Overcoming the Challenges of Multi-die Systems Verification”
Lauro Rizzatti, hardware-assisted verification consultant, served as moderator for a well-attended and lively 2024 DVCon U.S. panel discussion on the challenges in multi-die systems verification.
The hour-long session featured panelists Alex Starr, AMD Corporate Fellow; Bharat Vinta, Director of HW Engineering at Nvidia; Divyang Agrawal, Sr. Director of RISC-V Cores at Tenstorrent; and Arturo Salz, Synopsys Fellow.
What follows is a shortened panel transcript, edited for readability.
Lauro
How is multi-die evolving and growing? More specifically, what advantages have you experienced? Any drawback you can share?
To read the full article, click here
Related Chiplet
- Automotive AI Accelerator
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
Related Blogs
- Why 2023 Holds Big Promise for Multi-Die Systems
- Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi-Die Systems
- TSMC Advanced Packaging Overcomes the Complexities of Multi-Die Design
- Using Voltus IC Power Integrity to Overcome 3D-IC Design Challenges
Latest Blogs
- The Growing Importance of Advanced Packaging in Europe – Recap of ERS TechTalk
- Cadence Silicon Success of UCIe IP on Samsung Foundry’s 5nm Automotive Process
- Ayar Labs Optical Connectivity for AI Compute Fabrics
- The APECS Pilot Line: Heterointegration enabling Chiplet Applications
- The Future of Faster, Smaller, and More Efficient Chips: A Breakthrough in Hybrid Bonding