Moderating Our Open Chiplet Enthusiasm. A NoC Perspective
February 14, 2024
I recently talked with Frank Schirrmeister (Solutions & Business Development, Arteris) on the state of progress to the open chiplet ideal. You know – where a multi-die system in package can be assembled with UCIe (or other) connections seamlessly connecting data flows between dies. If artificial general intelligence and industrial-scale quantum computing are right around the corner, surely any remaining issues in open chiplet design should be a snap to resolve? According to Frank, the answer is yes and no. For a couple of privileged groups, anything is possible and is being put into practice today. For larger open markets, not so much, at least not in the near term.
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Blogs
- Addressing the Colossal Challenge of System Co-Optimization with a Holistic Chiplet Design Methodology
- Accelerating Early-Stage explorations with Virtual Prototyping for a thriving multi-vendor chiplet ecosystem
- An Open Framework for exploring Architecture Interoperability driving multi-vendor Chiplet Eco-systems
- UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem
Latest Blogs
- Call for Participation (CFP) Open Framework for Chiplet Eco-system Virtual Prototyping
- Inside the Chiplet Revolution: How Arm’s Compute Subsystems Platform is Democratizing Custom AI Silicon
- The Chiplet Calculus: Navigating the Integration Crisis at the Hardware.AD Frontier
- Why Electrical Design Matters in Chiplet Architectures – Part Two: UCIe Latency and Security
- From Blocks to Systems: Understanding Chiplets in SoC Design