Interconnect Chiplet

The ML100 IO Die is a high-bandwidth memory solution that integrates efficient UCIe (Die-to-Die) interconnect IP and HBM3 IP. The UCIe IP follows the UCIe 1.1 Specification and supports both standard and advanced packaging technologies, offering up to 1 TB/s of transfer bandwidth in a single module configuration. The UCIe supports the AXI4.0 interface standard, enabling ultra-low latency, high-speed interconnectivity between two dies. And the integrated HBM3 IP adheres to the HBM3 JESD238 standard and supports IO transfer rates of up to 6400 Mbps.

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Block Diagram

Interconnect Chiplet Block Diagram