Five Workflows for Tackling Heterogeneous Integration of Chiplets for 2.5D/3D

By Kevin Rinebold, Siemens EDA
3dincites, April 15, 2024

Keeping pace with Moore’s law continues to be challenging and is driving the adoption of innovative packaging technologies that support continued system scaling while doing so at lower costs than comparable monolithic devices. 

These packaging technologies disaggregate what would typically be a homogenous, monolithic device — like an ASIC or system-on-chip (SoC) — into discrete, unpackaged dies, known as chiplets, specifically designed and optimized for operation within a package in conjunction with other chiplets (Figure 1). This is also referred to as heterogeneous integration (HI), where multiple dies or chiplets for 2.5D/3D are integrated into a system-in-package (SiP) design. 

Heterogeneously integrated SiP devices offer considerable benefits, including higher performance, lower power usage, smaller area, lower cost, and faster time to market. However, thus far they are designed and produced by only a small number of advanced users. Broad industry proliferation will require a standardization of chiplet models and die-to-die connectivity IP—efforts currently underway—supported by new workflows. 

This article will focus on five workflows that are essential for planning, implementing, verifying, and co-designing heterogeneous design of chiplets for 2.5D/3D. (Figure 2).

1. Architectural planning and analysis
2. Physical design planning and analysis
3. Design analysis
4. Reliability analysis
5. Test planning and validation

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