Analysis Of Multi-Chiplet Package Designs And Requirements For Production Test Simplification

UCIe helps test through a fixed shoreline, multiple redundant lanes, and mission mode lane performance monitoring.

By Vineet Pancholi, Amkor
SemiEngineering (November 21st, 2024)

In recent years there has been a sharp rise of multi-die system designs. Numerous publications targeting a large variety of applications exist in the public domain. One presentation [2] on the IEEE’s website does a good job of detailing the anecdotal path of multi-die systems by way of chiplet building blocks integrated within a single package [2]. The presentation includes references to a handful of example multi-die systems that include artificial intelligence (AI), central processing unit (CPU), field-programmable gate array (FPGA), memory,  analog, radio frequency (RF), input/output (I/O), serializer/deserializer (SERDES), silicon (Si) photonics, etc. It describes advantages and disadvantages of working with chiplets. In addition, it provides package design considerations, including functional and performance aspects. While it serves as good reference material for background, it provides little to no detail for testability. Chapter 8 of the Heterogeneous Integration Roadmap 2019 Edition offers additional packaging details on single chip and multi-chip integration [3].

Outsourced assembly and test (OSAT) houses are in a unique position in the industry since they experience a wide sampling of customer products. Higher volumes and higher mix of products result in a unique perspective of key learning points and missed steps for product packages with multiple die.

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