Die-Level Transformation of 2D Shuttle Chips into 3D-IC for Advanced Rapid Prototyping using Meta Bonding
May 22, 2025
Chiplet Technical Papers
STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration
May 15, 2025
MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules
May 11, 2025
FoldedHexaTorus: An Inter-Chiplet Interconnect Topology for Chiplet-based Systems using Organic and Glass Substrates
April 30, 2025
ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification
April 29, 2025
ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC
April 28, 2025
Advanced Chiplet Placement and Routing Optimization considering Signal Integrity
April 24, 2025
Building Advanced 3D Devices with DBI®
April 17, 2025
PPAC Driven Multi-die and Multi-technology Floorplanning
April 8, 2025
Taking 3D IC Heterogeneous Integration Mainstream
March 27, 2025
CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems
March 25, 2025
Three-dimensional photonic integration for ultra-low-energy, high-bandwidth interchip data links
March 24, 2025
Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging
March 21, 2025
ARCAS: Adaptive Runtime System for Chiplet-Aware Scheduling
March 18, 2025
Fulfilling 3D-IC Trade-Off Analyses (And Benefits) With An AI Assist
March 13, 2025
Garblet: Multi-party Computation for Protecting Chiplet-based Systems
March 12, 2025
Speeding Down Memory Lane With Custom HBM
March 11, 2025
Multi-Die Health and Reliability: Synopsys and TSMC Showcase UCIe Advances
March 7, 2025
REED: Chiplet-based Accelerator for Fully Homomorphic Encryption
March 5, 2025
Signal Integrity Challenges in Chiplet-Based Designs: Addressing Performance and Security
March 4, 2025
