PPAC Driven Multi-die and Multi-technology Floorplanning

By Cristhian Roman-Vicharra¹, Yiran Chen², Jiang Hu^1,3

Abstract

In heterogeneous integration, where different dies may utilize distinct technologies, floorplanning across multiple dies inherently requires simultaneous technology selection. This work presents the first systematic study of multi-die and multi-technology floorplanning. Unlike many conventional approaches, which are primarily driven by area and wirelength, this study additionally considers performance, power, and cost, highlighting the impact of technology selection. A simulated annealing method and a reinforcement learning techniques are developed. Experimental results show that the proposed techniques significantly outperform a naïve baseline approach.

Index Terms: 

heterogeneous integration, PPAC, floorplanning

I. Introduction

Heterogeneous integration (2.5D and 3D-IC) opened up opportunities for building complex IC designs into a single chip with applications in high-performance computing, 5G technology, artificial intelligence, etc. One key aspect of heterogeneous integration compared to monolithic IC designs is that multiple dies of different manufacturing process technologies are integrated into a single system, allowing the re-usability of already designed IPs that are otherwise difficult to redesign in a smaller technology. Heterogeneous integrations also achieve enhanced functionality, compact area and design flexibility.

Multi-die floorplanning plays a critical role in determining die area, global interconnect, thermal and warpage, which have been the main focus of existing methods. In [1], a simulated annealing-based multi-die floorplanning technique is proposed for minimizing area and wirelength with consideration of IO assignment. A floorplanning that considers multi-die interconnect bridge assignments is proposed in [2] based on simulated annealing, targeting bounding area and wirelength. A die placement work is introduced in [3] for minimizing wirelength through a branch-and-bound approach. A thermal-driven die placement technique based on simulated annealing is introduced in [4]. Another die placement work [5] is mainly targeted to addressing the warpage issue. A thermal-driven chiplet floorplan using reinforcement learning is reported in [6]. A reinforcement learning approach to 3D floorplanning is proposed in [7] for wirelength, routability and thermal optimization. The work of [8] considers warpage, cost and performance as objectives during the floorplanning by proposing a more elaborated methodology based on a mathematical programming formulation. Even so, power consumption and technology selection is left aside.

In heterogeneous integration, assigning a circuit block to different dies often implies simultaneous selection of different technologies. As a result, a circuit block may exhibit significantly different performance, power, and area characteristics depending on the die it is placed on. While the challenges of multi-die and multi-technology floorplanning have been acknowledged in [9], to the best of our knowledge, little to no prior research addressing this problem comprehensively.

In this work, we present a methodology for multi-die and multi-technology floorplanning (MMFP). Our approach optimizes multiple objectives, including performance (measured by total negative slack), power, area, die cost, and total wirelength, accounting for both intra-die and inter-die connections. The input to our MMFP can accommodate both soft IPs in synthesizable HDL code and hard IPs with layouts. A notable feature of our MMFP is the use of recent machine learning techniques [10] for technology-specific PPA (Performance, Power, Area) estimation of circuit blocks. Two optimization techniques are studied: simulated annealing and reinforcement learning. Experimental results demonstrate that our MMFP consistently outperforms a naïve method across all objectives.

The key contributions of this work are summarized as follows:

• To the best of our knowledge, this is the first study on multi-die and multi-technology floorplanning.
• Two optimization techniques are studied, simulated annealing and reinforcement learning.
• We demonstrate that the concurrent technology selection and its impact on circuit PPA can be effectively addressed by leveraging a recent ML technique.
• Experimental results based on post-placement analysis using commercial tool show that our RL method outperforms a naïve method by 21.7% in TNS, 8.1% in power, 12% in wirelength, 8.8% in area, and 5.7% in cost.
• Ablation study results confirm that our MMFP method achieves different PPAC tradeoffs and accommodate both soft and hard IPs.

Our future studies will additionally consider thermal and warpage issues. The rest of this paper is organized as follows. Previous related works are briefly reviewed in Section II. The background knowledge relevant to our work is presented in Section III. Section IV provides the problem formulation. Our MMFP techniques are described in Section V. Experimental results are covered in Section VI. Finally, Section VII presents the conclusions.

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