Thermal Comparison between Monolithic and Chiplet ASIC Design

As Moores law approaches the physical limit of the critical size on chip, the need for the use of domain-specific accelerators (DSA) to meet power and performance has been increased. Advanced packaging is used to achieve higher integration densities and performance. However, managing  package thermal density is becoming challenging for accelerators and ASIC. In order to understand the thermal density trade off for die disaggregation advanced package solutions (2D, 2.5D, 3D), this paper selects a ASIC die with compute and SRAM as an example. This talk will focus on understanding the change in thermal density of a package from monolithic die to advanced packaging with chiplet die with 2D, 2.5D, and 3D package options and partner with ecosystem to understand the thermal solution (lid vs. lidless). The thermal performance among the different package options as well as the thermal risks and solutions are discussed in this paper.