Cost And Quality Of Chiplets
Chiplets add a whole new challenge for the semiconductor industry. How much testing is enough? How do you optimize system binning? What’s the right amount of burn-in? The answers to these questions will vary, depending upon cost and quality tradeoffs, the number and source of the chiplets, and real-world workloads and projected lifespans. Marc Jacobs, senior director of solutions architecture at PDF Solutions, talks with Semiconductor Engineering about the importance of collecting and analyzing data in heterogeneous designs, as well as the need to get it to the testers at the precise moment because not everything needs to be tested the same way.
Related Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
Related Videos
- IBM Research: Benefits and challenges of Chiplets
- Surface codes and modular chiplets in the presence of defects
- Investigating Chiplets for Scalable and Cost Effective HPC Beyond Exascale
- Revolutionizing System Design: Impact of Chiplets and Heterogeneous Integration on AI Server
Latest Videos
- Mick Posner talks about the importance of UCIe
- Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
- Speeding Up Die-To-Die Interconnectivity
- GENIOEVO™ – Architectural Exploration and Connectivity Management in Advanced Packaging
- Enabling a true open ecosystem for 3D IC design