Chiplet based Reconfigurable OCP Accelerator Module (OAM) architecture and platform
By Suresh Subramaniam, Distinguished Engineer - Packaging and Systems, Apex Semiconductor
In this talk, we will expand on a previous talk and outline a chiplet based Reconfigurable Open Compute Accelerator Module (ROAM) platform. In OAI, reuse, scalability, and modularity of hardware is defined up until the OAM. This new platform leverages existing OAI infrastructure and extends this into advanced packaging and chiplets. We will outline the specifics of a System in Package (SiP) which includes a standard footprint for attaching the SiP to the ROAM base board. The SiP will also have standard footprints to house up to 8 domain specific accelerators (DSA) chiplets, IO chiplets, and hub/bridge/switch chiplets. Standardization of the chiplet footprints enables a highly modular, scalable , ROAM platform. Furthermore, it enables innovation in DSA offerings by providing clear power, performance and area specifications. This platform has the potential to usher in the era of Plug and Play Chiplets (PnPC). High degree of composability enables targeted microservices.
Related Videos
- Chiplet Architecture Accelerates Delivery of Industry-Leading Intel® FPGA Features and Capabilities
- D2D Chiplet Based SiP Testing Challenges and Solutions
- Paving the Road Ahead: RISC-V and Chiplet Technologies in Modern Automotive and Data Center Architectures
- Architecting Next Generation Compute and I/O Chiplet for AI/ML, Cloud and Edge Platforms
Latest Videos
- Accelerating AI Innovation with Arm Total Design: A Case Study
- The Rise of The Hublet™ & FPGA Chiplets
- From Internal Designs to Open Chiplet Economy: Discussion on How to Create Open, Democratized Access to Chiplet Technology
- “Dating” and “Marrying”: An AI Chiplet’s Perspective
- Impact of Chiplets, Heterogeneous Integration and Modularity on AI and HPC systems