World’s first UCIe heterogeneous chiplet test chip
By Nick Flaherty, eeNews Europe (December 18, 2023)
Synopsys and Intel have developed the first test chip with the Universal Chiplet Interconnect Express (UCIe) protocol used to connect chiplets made on different processes.
The test chip demonstrated UCIe traffic between Synopsys UCIe PHY IP and Intel UCIe PHY IP, simulating each test chip using the Synopsys VCS functional verification tool.
Intel’s test chip, Pike Creek, consists of an Intel UCIe IP chiplet fabricated on Intel 3 technology and was paired with a Synopsys UCIe IP test chip fabricated on the TSMC N3 process. The successful pairing mimics the mixing and matching of dies that can occur in real-world multi-die systems, demonstrating that this approach is commercially viable.
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- BoS Semiconductors joins UCIe Consortium for its ADAS chiplet SoC family
- PseudolithIC Inc. Raises $6M in Seed Funding to Revolutionize Wireless Chips with Proprietary Chiplet Heterogeneous Integration Technology
- Ayar Labs Unveils World's First UCIe Optical Chiplet for AI Scale-Up Architectures
- Analogue Insight and Tetrivis Announce Joint Development of “Eurytion RFK1”, a UCIe based 12 nm Ka/Ku-Band RF Chiplet Transceiver
Latest News
- Intel’s Expanding IP Portfolio in Co-Packaged Optics
- Rebellions Scales Global Growth with Silicon Valley backed Series C
- Rebellions Accelerates Global Expansion and Strengthens Customer-centric Strategy with Significant Executive Appointments
- Tower Semiconductor Announces New CPO Foundry Technology Available On Tower’s Leading Sipho and EIC Optical Platforms
- How Advanced Packaging is Unleashing Possibilities for Edge AI