World’s first UCIe heterogeneous chiplet test chip
By Nick Flaherty, eeNews Europe (December 18, 2023)
Synopsys and Intel have developed the first test chip with the Universal Chiplet Interconnect Express (UCIe) protocol used to connect chiplets made on different processes.
The test chip demonstrated UCIe traffic between Synopsys UCIe PHY IP and Intel UCIe PHY IP, simulating each test chip using the Synopsys VCS functional verification tool.
Intel’s test chip, Pike Creek, consists of an Intel UCIe IP chiplet fabricated on Intel 3 technology and was paired with a Synopsys UCIe IP test chip fabricated on the TSMC N3 process. The successful pairing mimics the mixing and matching of dies that can occur in real-world multi-die systems, demonstrating that this approach is commercially viable.
To read the full article, click here
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- System-level UCIe IP for early architecture analysis of 3D Chiplet Design and Packaging
- OPENEDGES Unveils UCIe Chiplet Controller IP, Expanding Design Portfolio
- BoS Semiconductors joins UCIe Consortium for its ADAS chiplet SoC family
- PseudolithIC Inc. Raises $6M in Seed Funding to Revolutionize Wireless Chips with Proprietary Chiplet Heterogeneous Integration Technology
Latest News
- Untether AI Enters Into a Strategic Agreement with AMD
- Alphawave Semi Tapes Out Breakthrough 36G UCIe™ IP on TSMC 2nm, Unlocking Foundational AI Platform IP on Nanosheet Processes
- How Secure Are Analog Circuits?
- Sarcina Technology advances photonic package design to address key data center challenges
- Imec demonstrates 16nm pitch Ru lines with record-low resistance obtained using a semi-damascene integration approach