CDimension Launches to Tackle Hardware Bottlenecks from the Ground Up, Beginning with Commercial 2D Materials Release
Debut of ultra-thin materials delivers up to 1,000× energy efficiency improvements, a foundational step toward vertically integrated chips that unify compute, memory, and power
SAN JOSE, Calif.-- July 17, 2025 --CDimension, a company building foundational computing hardware, today announced the commercial availability of its ultra-thin 2D semiconductor materials, marking a key milestone in bringing lab-scale innovation into practical, scalable use. These materials are now available for commercial sampling and integration, already being evaluated by early customers, and represent the first visible step toward CDimension’s long-term vision of vertically integrated chips that unify compute, memory, and power into a single, high-efficiency system.
As AI, robotics, quantum computing, and edge workloads grow in complexity, traditional silicon-based architectures are hitting physical and architectural limits. Rising energy costs, slower data transfer, and fragmented chiplet packaging are constraining progress across industries. CDimension is solving these challenges at the foundation, starting with new materials and leading toward a monolithic 3D architecture based on atomically-thin chiplets designed to deliver up to:
- 100× higher energy efficiency
- 100× improvement in integration density
- 10× higher system-level operating frequency through reduced parasitic
Founded by Jiadi Zhu, an MIT Ph.D. in electrical engineering with deep expertise in 2D materials and monolithic 3D integration, advised by MIT professor Tomás Palacios, director of the Microsystems Technology Laboratories and a global leader in electronic materials, CDimension combines deep technical innovation with a clear roadmap for real-world deployment.
“The world’s demand for computational power is accelerating faster than traditional hardware can evolve,” said Zhu, founder and CEO of CDimension. “We’re no longer limited by chip architecture alone—we’re constrained by the physical materials themselves. To move forward, we must rebuild the foundation. That’s why we’re focused on developing disruptive technologies in new materials and 3D integration methods that redefine efficiency, density, and performance for next-generation systems.”
At the core of the company’s commercial debut is a proprietary low-temperature process that enables the direct growth of ultra-thin 2D materials, such as molybdenum disulfide (MoS2), onto finished silicon wafers without damaging underlying circuitry. The resulting layers are atomically thin, low-leakage, and energy efficient, supporting dense vertical stacking and enabling new levels of integration. While 2D materials have long held promise for next-generation chips, adoption has been slowed by manufacturing and integration hurdles. CDimension’s process overcomes these challenges with a Si back-end-of-line (BEOL) compatible approach that supports uniform, wafer-scale monolayer film growth across full silicon wafers, a key step in moving 2D materials from lab experiments to scalable commercial use. In internal testing, CDimension’s materials have demonstrated up to a 1,000× improvement in transistor-level energy efficiency compared to silicon.
“2D materials have enormous potential in many areas especially for semiconductor industry and future computing, and the development of successful wafer scale synthesis is the key to unlock many of these possibilities for the future,” said Jing Kong, faculty member at MIT. “It is great to see CDimension builds upon their former work on low temperature wafer-scale MoS2 synthesis to make not only these monolayer materials but also the overall BEOL compatible process available. This will open up entirely new design architectures for memory, power, and AI computing systems that were previously impractical.”
In addition to MoS2, CDimension provides a full suite of high-quality 2D materials, including n-type, p-type, metallic, and insulating films, via a wafer-scale deposition process compatible with silicon manufacture. This allows seamless integration with existing manufacturing workflows and forms the materials backbone of CDimension’s broader vision to unify compute, memory, and power in a single chip architecture.
CDimension’s 2D materials are now available for commercial sampling and integration at research-accessible cost. Early customers across industry and academia are already evaluating the technology in production-relevant settings and the company is expanding access to additional research and development teams.
To support early adopters, CDimension also offers customized services through its Premier Membership program, including monolayer deposition over 3D structures and on up to 12-inch arbitrary substrates for prototyping and fabricating 2D-material-based circuits.
While 2D materials are CDimension’s first commercial release, they are just the beginning. The company’s vertically integrated architecture is designed to deliver system-wide performance gains through monolithic 3D integration and localized power management. CDimension holds multiple patents and patent applications across its materials, integration methods, and chip architectures, giving system builders the hardware foundation they need to overcome today’s bottlenecks and scale for tomorrow’s demands.
For more information or to request materials, visit www.cdimension.com.
About CDimension
CDimension is a company building foundational computing hardware, developing faster, smarter, and more compact systems to meet the demands of modern computing. With an innovative approach and patented technology, CDimension combines wafer-scale synthesis of ultra-thin materials, monolithic 3D integration, and efficient power management to deliver high-performance solutions that improve efficiency, reduce energy use, and lower system costs. The company was founded by Jiadi Zhu, an MIT Ph.D. focused on semiconductor systems for energy-efficient computing. Tomás Palacios, an MIT professor and global expert in advanced electronic materials and devices, serves as the strategic advisor.
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- Fraunhofer IIS/EAS Selects Achronix Embedded FPGAs (eFPGAs) to Build Heterogeneous Chiplet Demonstrator
- Gartner Forecasts Worldwide Semiconductor Revenue to Grow 17% in 2024
- TOPPAN to Build Line for Development and Mass Production of Next-Generation Semiconductor Packages in Ishikawa, Japan
- Can Chiplets Solve Semiconductor Challenges?
Latest News
- CDimension Launches to Tackle Hardware Bottlenecks from the Ground Up, Beginning with Commercial 2D Materials Release
- Ayar Labs Strengthens Leadership Team and Expands Global Presence to Accelerate High Volume Co-Packaged Optics
- When Can I Buy A Chiplet?
- Rigetti Demonstrates Industry’s Largest Multi-Chip Quantum Computer; Halves Two-Qubit Gate Error Rate
- InPsytech Tapes Out F2F SoIC Design Compliant with UCIE 2.0 Standard Enabling High-Speed Interconnects for 3D Heterogeneous Integration