TSMC drives A16, 3D process technology
By Nick Flaherty, eeNews Europe (November 20, 2024)
TSMC is looking to introduce its A16 1.6nm process by the end of 2026 with an IEEE standard for its 3Dblox technology.
The Open Innovation Platform (OIP) meeting in the Netherlands this week showed that the 2nm process will be in production in 2025 following early tapeouts this year, with a variant called N2P nanoFlex with the option for short standard cells for smaller area and greater power efficiency or tall cells for more performance.
This will give a 12% boost in energy efficiency over the base 2nm process, while A16 will give a 30% boost with the same density as N2 nanoFlex. Both TSMC and Intel are detailing their 2nm technologies at the IEDM conference in December.
Related Chiplet
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
- UCIe based 12-bit 12-Gsps Transceiver
Related News
- TSMC to Provide 3DIC Integration for AI Chips in 2027, Featuring 12 HBM4 and Chiplets Manufactured with A16
- Chiplet Pioneer Eliyan Achieves First Silicon in Record Time with Implementation in TSMC 5nm Process, Confirms Most Efficient Chiplet Interconnect Solution in the Multi-Die Era
- TSMC Announces Breakthrough Set to Redefine the Future of 3D IC
- TSMC plans automotive chiplet process for 2025
Latest News
- Intel Announces Retirement of CEO Pat Gelsinger
- Rebellions and SAPEON Korea Complete Merger, Launching Korea’s First AI Chip Unicorn
- MZ Technologies unveils roadmap for its integrated chiplet/packaging Co-Design EDA tool
- Top-Down Vs. Bottom-Up Chiplet Design
- Alphawave Semi Drives Innovation in Hyperscale AI Accelerators with Advanced I/O Chiplet for Rebellions Inc