New Tradeoffs In Leading-Edge Chip Design
By Katherine Derbyshire, Semiconductor Engineering (November 21st, 2024)
Device design begins with the anticipated workload. What is it actually supposed to do? What resources — computational units, memory, sensors — are available?
Answering these questions and developing the functional architecture are the first steps in a new design — well before committing it to silicon, said Tim Kogel, senior director of technical product management at Synopsys. Yet even these early decisions begin to constrain the physical architecture.
With a model of the proposed functionality, planners can begin to ask ‘what if’ questions. Does increasing on-chip memory improve performance enough to justify the increased cost and silicon area? What type of GPU is the best match for the anticipated workload?
To read the full article, click here
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- Arm Chiplet System Architecture Makes New Strides in Accelerating the Evolution of Silicon
- Signal Integrity Plays Increasingly Critical Role In Chiplet Design
- Intel Unveils Chiplet Alliance To Enable New Chip Designs
- Cadence Accelerates SoC, 3D-IC and Chiplet Design for AI Data Centers, Automotive and Connectivity in Collaboration with Samsung Foundry
Latest News
- Siemens streamlines design and analysis of complex, heterogeneously integrated 3D ICs
- Bruker Experiences Growth in Semiconductor Advanced Packaging Market Fueled by AI Demands
- 2.5D/3D chip technology to advance semiconductor packaging
- Arteris Addresses Silicon Design Reuse Challenge with New Magillem Packaging Product for IP Blocks and Chiplets
- EU Project ELENA Pioneers LNOI Platform for Next-Gen Photonic Circuits & Europe’s 1st Commercial Supplier of LNOI Wafers