Chiplets Still A Challenge With UCIe 2.0
New connectivity standard brings performance improvements and a bunch of new features, but it may take years before they are adopted — and still may not result in an open chiplet market.
By Brian Bailey, Semi Engineering (January 30, 2025)
Plug-and-play chiplets are a popular goal, but does UCIe 2.0 move us any closer to that becoming a reality? The problem is that the current drivers of the standard are not after interoperability in the way that plug-and-play requires.
Released in August 2024, UCIe 2.0 touts higher bandwidth density and improved power efficiency, as well as new features supporting 3D packaging, a manageable system architecture, and more. The standard is being driven by key industry leaders, including ASE, Alibaba, AMD, Arm, Google Cloud, Intel, Meta, Microsoft, NVIDIA, Qualcomm, Samsung Electronics, and TSMC.
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- QuickLogic and YorChip Partner to Develop Low-Power, Low-Cost UCIe FPGA Chiplets
- For the First Time, UCIe Shares Bandwidth Speeds Between Chiplets
- How do UCIe and BoW interconnects support generative AI on chiplets?
- How does UCIe on chiplets enable optical interconnects in data centers?
Latest News
- Socionext and imec Update Core Partner Program
- TCS Unveils Chiplet-Based System Engineering Services to Accelerate Semiconductor Innovation
- Deca and Silicon Storage Technology Announce Strategic Collaboration to Enable NVM Chiplet Solutions
- Lam Research Introduces VECTOR® TEOS 3D to Address Critical Advanced Packaging Challenges in Chipmaking
- Scintil Photonics Raises $58M to Scale Integrated Photonics for AI Factories