Chiplets Still A Challenge With UCIe 2.0
New connectivity standard brings performance improvements and a bunch of new features, but it may take years before they are adopted — and still may not result in an open chiplet market.
By Brian Bailey, Semi Engineering (January 30, 2025)
Plug-and-play chiplets are a popular goal, but does UCIe 2.0 move us any closer to that becoming a reality? The problem is that the current drivers of the standard are not after interoperability in the way that plug-and-play requires.
Released in August 2024, UCIe 2.0 touts higher bandwidth density and improved power efficiency, as well as new features supporting 3D packaging, a manageable system architecture, and more. The standard is being driven by key industry leaders, including ASE, Alibaba, AMD, Arm, Google Cloud, Intel, Meta, Microsoft, NVIDIA, Qualcomm, Samsung Electronics, and TSMC.
To read the full article, click here
Related Chiplet
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
- UCIe based 12-bit 12-Gsps Transceiver
Related News
- QuickLogic and YorChip Partner to Develop Low-Power, Low-Cost UCIe FPGA Chiplets
- For the First Time, UCIe Shares Bandwidth Speeds Between Chiplets
- How do UCIe and BoW interconnects support generative AI on chiplets?
- How does UCIe on chiplets enable optical interconnects in data centers?
Latest News
- Chip Architectures Becoming Much More Complex With Chiplets
- Chiplets Still A Challenge With UCIe 2.0
- Advanced Packaging Moving At Breakneck Pace
- OKI Achieves 3D Integration of Thin-Film Analog ICs Using CFB Technology in Collaboration with Nisshinbo Micro Devices
- Automotive Chiplet Ecosystem Heralds Agility and Flexibility