For the First Time, UCIe Shares Bandwidth Speeds Between Chiplets

By Agam Shah, HPC Wire (June 7, 2023)

The first numbers of the available bandwidth between chiplets are out – UCIe is estimating that chiplet packages could squeeze out communication speeds of 630 GB/s, or 0.63 TB/s, in a very tight area.

That number was shared by the Universal Chiplet Interconnect Express consortium last month during a presentation at ISC 2023. The consortium is developing UCIe, which is emerging as a universal interconnect to connect different silicon modules on a chiplet package.

Chip designers and manufacturers are breaking up big chip design into small pieces via chiplets, which are silicon modules that are assembled in one package. The chiplet approach can combine a wide range of accelerators and technologies in a single package. The current approach of throwing everything in one integrated chip is becoming cost prohibitive.

Chiplets are also beneficial by enabling silicon made on different nodes to be packaged together. For example, mixed signal chiplets made on older nodes could be combined with dense subsystems made on newer process nodes.

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