Advanced packaging blurs line between monolithic chip and packaged assembly of heterogeneous chips: NAPMP NoI
By Pradeep Chakraborty, Pradeep’s TechPoints (July 17, 2024)
Dr. Subramanian S. Iyer, Senior Technical Advisor, CHIPS NAPMP, recently provided the notice of intent (NoI).
National Advanced Packaging Manufacturing Program (NAPMP) will drive US leadership in advanced packaging and provide the technology needed for packaging manufacturing in the United States. NAPMP will develop critical and relevant innovations for advanced packaging technologies and accelerate their scaled transition to US manufacturing entities.
Within a decade, NAPMP-funded activities, coupled with CHIPS manufacturing incentives, will establish a vibrant, self-sustaining, profitable, high-volume, domestic, advanced packaging industry where advanced-node chips manufactured in the U.S. are packaged in the U.S. We expect the technology developed to be leveraged in new applications and market sectors and at scale.
Packaging roadmaps include NIST-sponsored roadmaps such as MRHIEP, MAESTRO, and MAPT. Other roadmaps include HIR and IRDS. All aspects of technologies are required to develop leading-edge onshore advanced packaging manufacturing capability.
To read the full article, click here
Related Chiplet
- Automotive AI Accelerator
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
Related News
- Biden-Harris Administration Announces CHIPS Incentives Awards with Absolics and Entegris to Support Development of Advanced Packaging Technology and Onshore Materials for Leading-Edge Chip Production
- Enosemi and Jabil to develop advanced packaging process technology for photonic chips
- The Era of Heterogeneous Integration Approaches: Who Shall Dominate the Advanced Packaging Field?
- SK hynix Signs Investment Agreement of Advanced Chip Packaging with Indiana
Latest News
- Major Advancement in Applied Research: FMD Launches the Chiplet Application Hub
- Baden-Württemberg attracts imec to lead development of chiplet-based technology for automotive applications
- Marvell Demonstrates Silicon Photonics Light Engine for Low-power, Rack-scale Interconnect in AI Networks
- Ranovus® announces collaboration with Jabil® for mass production of ODIN® optical engine
- Ayar Labs Unveils World's First UCIe Optical Chiplet for AI Scale-Up Architectures