Advanced packaging blurs line between monolithic chip and packaged assembly of heterogeneous chips: NAPMP NoI
By Pradeep Chakraborty, Pradeep’s TechPoints (July 17, 2024)
Dr. Subramanian S. Iyer, Senior Technical Advisor, CHIPS NAPMP, recently provided the notice of intent (NoI).
National Advanced Packaging Manufacturing Program (NAPMP) will drive US leadership in advanced packaging and provide the technology needed for packaging manufacturing in the United States. NAPMP will develop critical and relevant innovations for advanced packaging technologies and accelerate their scaled transition to US manufacturing entities.
Within a decade, NAPMP-funded activities, coupled with CHIPS manufacturing incentives, will establish a vibrant, self-sustaining, profitable, high-volume, domestic, advanced packaging industry where advanced-node chips manufactured in the U.S. are packaged in the U.S. We expect the technology developed to be leveraged in new applications and market sectors and at scale.
Packaging roadmaps include NIST-sponsored roadmaps such as MRHIEP, MAESTRO, and MAPT. Other roadmaps include HIR and IRDS. All aspects of technologies are required to develop leading-edge onshore advanced packaging manufacturing capability.
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- Biden-Harris Administration Announces CHIPS Incentives Awards with Absolics and Entegris to Support Development of Advanced Packaging Technology and Onshore Materials for Leading-Edge Chip Production
- ASE Expands its Chip Packaging and Testing Facility to Enable Next-Gen Applications
- Enosemi and Jabil to develop advanced packaging process technology for photonic chips
- YES Selected to Deliver Full Portfolio of Advanced Packaging Tools for Glass Panel AI and HPC Applications by a Leading AI Infrastructure Supplier
Latest News
- BOS Semiconductors and Tenstorrent Partner to Build an Open Chiplet Ecosystem
- Astera Labs to Acquire aiXscale Photonics
- YorChip announces Universal PHY™ PPA and introduces Open PHY to jumpstart broader market
- PGC Integrates 2.5D/3D Advanced Packaging Technology to Break the “Memory Wall” and Accelerate AI/HPC ASIC Innovation
- Tenstorrent Announces Open Chiplet Atlas™ Ecosystem to Accelerate and Standardize an Open Chiplet Ecosystem