Why the World Needs an Integrated Chiplet-to-Wafer Hybrid Bonder

By Amulya Athayde

September 22, 2025

In response to escalating computation demand for artificial intelligence, the semiconductor industry has embraced heterogeneous integration technologies to develop advanced accelerators. These solutions consolidate CPU, GPU, memory, input/output, and power management functionalities within a single package. The process involves separating logic, memory, and other components into distinct dies or chiplets, which are subsequently assembled using high-density, low-latency, and low-resistance interconnects. This approach improves both electrical and thermal performance and contributes to reduced power consumption.

In common practice, chiplets are connected via microbumps, which consist of metal studs topped with solder balls. Chiplets equipped with microbumps are positioned together and heated in a reflow oven, melting the solder to establish interconnections; alternatively, thermal compression bonding may be used, applying pressure and heat to bond each chiplet. Microbump interconnects are typically arranged at a pitch between 25 and 50 microns, allowing for an interconnect density of several hundred per square millimeter. Optimizing bump design and bonding techniques can further increase this density to several thousand per square millimeter, which is significant for high-bandwidth communication between small devices.

Microbump limitations are influenced by physical and material constraints. Reducing bump size and increasing density are affected by solder connection effectiveness – excess solder may result in bridging or shorts between adjacent bumps, while insufficient solder can leave open connections. Reliability at smaller scales is impacted by the formation of copper post and solder intermetallic compounds, which have different thermo-mechanical properties that can cause cracking and mechanical failures.

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