The Future of Faster, Smaller, and More Efficient Chips: A Breakthrough in Hybrid Bonding

By JoAnn Yamani

March 3, 2025

Imagine a world where our computers, smartphones, and artificial intelligence (AI) systems operate even faster while consuming less power. One of the key innovations making this future possible is hybrid bonding, a cutting-edge technology that enables ultra-efficient stacking of microchips. Researchers at Adeia have been refining this process to ensure it meets the demands of the semiconductor industry. In this article, we’ll explain their latest advancements in making hybrid bonding cleaner and more reliable.

What is Hybrid Bonding and Why Does It Matter?

Modern advanced packages are becoming increasingly complex, with high bandwidth memory (HBM)—the backbone of AI and high-performance computing—requiring multiple layers of microchips stacked together. Traditionally, these chips are connected using tiny solder bumps, but this method comes with several drawbacks, such as increased thickness, inefficient heat dissipation, and electrical resistance.

Hybrid bonding eliminates these issues by creating a direct, molecular-level connection between chips, making them thinner, faster, and more efficient. However, to achieve this, the surface of the chips must be perfectly clean and smooth—even microscopic contamination can ruin the connection. That’s where Adeia’s research comes in.

The Challenge: Keeping Chip Surfaces Spotless

When forming 3D stacks of HBM, the die must be thinned to less than or equal to ~50 um. The thinning process requires temporarily attaching a carrier wafer to hold the delicate wafer. This requires adhesives, but once processing is complete, these adhesives must be completely removed before hybrid bonding.

The problem? Traditional temporary bond materials and cleaning methods, which work fine for older solder-based bonding, leave microscopic residue and damage that can ruin hybrid bonding connections and the overall die stack. Adeia set out to solve this by developing a more advanced, environmentally friendly cleaning process.

The Solution: A New Cleaning Method

Adeia compared two different cleaning methods:

1. Solvent-based cleaning developed for solder-based bonding: This method uses chemicals to dissolve the adhesive, but it damages the copper pads needed for bonding and leaves tenacious contaminants on the surface.
2. Adeia’s new non-solvent cleaning: This eco-friendly process removes adhesive without damaging the copper pads or leaving residue.

Their results showed that traditional solvent-based cleaning compatible with solder-based bonding created too much damage and contamination, making it incompatible with hybrid bonding. In contrast, Adeia’s new cleaning method produced a pristine surface ideal for reliable chip stacking.

Why This Breakthrough Matters

By perfecting this new cleaning process, Adeia has made die-to-wafer hybrid bonding more viable for mass production, ensuring:

- Smaller, thinner chips that enhance mobile devices and AI processors.
- Improved performance by reducing electrical resistance and heat buildup.
- Higher manufacturing yield, meaning more functional chips per batch.
- Environmentally friendly production by eliminating harmful solvents.

This advancement is a game-changer for the semiconductor industry and a major step toward the next generation of faster, more powerful computing.

What’s Next?

Adeia’s research isn’t stopping here. Researchers plan to further refine their cleaning process and expand testing to more adhesive materials. As hybrid bonding becomes the standard for chip manufacturing, Adeia’s fundamental process development work plays an important role in qualifying materials and processes for the eventual high-volume manufacturing (HVM) ramp that our customers will need.  

The bottom line? Thanks to these innovations, we’re one step closer to a world where AI, cloud computing, and high-performance devices can reach their full potential – while staying cool, efficient, and lightning-fast.

Dr. Guilian Gao is presenting the paper that is the basis for this blog at the IMAPS, Device Packaging Conference on March 3-6, 2025.