The IOHub. An Emerging Pattern for System Connectivity in Chiplet-Based Designs
In chiplet-based design we continue the march of Moore’s Law by scaling what we can put in a semiconductor package beyond the boundaries of what we can build on a single die. This style is already gaining traction in AI applications, high performance computing, and automotive, each of which aims to scale out to highly integrated systems meeting performance, power, cost, and reliability goals. The technology challenge then is to build effective communications infrastructure between those chiplets.
UCIe is mentioned frequently as the standard for connectivity between chiplets. That standard is important, but is only the bottom layer of the communication stack. In the modern era of networks-on-chip (NoCs), modern networks must also handle packetized communication, congestion, and quality of service, within chiplets and between chiplets. This prompts a deeper dive into Arteris’ recently announced collaboration with AMD, in which FlexGen smart NoC IP cooperates with AMD’s Infinity Fabric. Commercial and proprietary network co-existence has arrived.
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Blogs
- Introduction to Chiplets: Why the Industry is Moving Beyond Monolithic Designs
- Optimizing IP Management for Chiplet-Based Designs
- Alphawave Semi Bridges from Theory to Reality in Chiplet-Based AI
- AI System Connectivity for UCIe and Chiplet Interfaces Demand Escalating Bandwidth Needs
Latest Blogs
- Introduction to Chiplets: Why the Industry is Moving Beyond Monolithic Designs
- What Happened at the 2025 OCP Global Summit?
- A look back at the Automotive Chiplet Forum 2025
- Accelerating an Open Chiplet Ecosystem for Automotive with Foundation Chiplet System Architecture
- A Guide to Building Chiplets Today While Shaping Tomorrow’s Standards