How 40G UCIe IP Powers Data Center AI Chips

By Manuel Mota

September 10, 2024

With physical limitations slowing Moore’s law and AI pushing the limits of technology, compute requirements and the demand for more processing power have grown exponentially. Modern data centers now require multi-die designs to power generative AI applications, driving many technology requirements including high-bandwidth and low-power die-to-die connectivity.

To ensure multi-die design success, the Universal Chiplet Interconnect Express (UCIe) specification streamlines die-to-die connectivity in multi-die designs by prioritizing interoperability, keeping latency down, enabling disparate dies to communicate with each other, and more.

Synopsys continues to stand at the forefront of the UCIe evolution. From teaming up with Intel on the world’s first successful UCIe interoperability test chip demonstration to launching a 40G UCIe solution with controller, PHY, and verification IP, Synopsys has empowered technology visionaries with a comprehensive and scalable multi-die solution from early architecture exploration to manufacturing.

Now, Synopsys is building on its mature and heavily adopted UCIe IP solution to address customer needs for maximum bandwidth and energy efficiency with the 40G UCIe IP.

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