RISC-V Chiplets, Disaggregated Die, and Tiles
Scalable High-Performance Computing SoC Design with RISC-V
Whether you refer to the design concept as a disaggregated die, tiles, chiplets, or good ol’ multi-chip modules, a growing trend among SoC designers is making the interposer act like a ‘mainboard’ to host multiple chips. Together, these chips form a coherent whole product intended for a specific market and offer both advanced workload performance and efficiency benefits.
The technology industry is shifting to custom designs, replacing traditional general-purpose CPU and discrete accelerator platforms. Instead, the computing platform can implement application-specific processing requirements at many levels, down to the instruction set architecture (ISA). Enabling this industry shift is central to SiFive’s mission and why SiFive’s founders invented RISC-V a decade ago.
To read the full article, click here
Related Chiplet
- Automotive AI Accelerator
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
Related Blogs
- RISC-V and Chiplets: A Panel Discussion
- Why Chiplets and why now?
- What are Chiplets and how they Assemble Into the Most Advanced SoCs
- How Disruptive will Chiplets be for Intel and TSMC?
Latest Blogs
- TSMC Brings Packaging Center Stage with Silicon
- Four Reasons Chiplets Will Take Over the World (and why it hasn’t happened yet)
- Breaking Through Bottlenecks: Executives from AMD, Ayar Labs, Cerebras, and Microsoft, Discuss the Future of AI Infrastructure with Optical I/O
- Lego-Style Software For Automotive And Industrial Chiplet Systems?
- Why Chiplets Are Key to Next-Gen Software-defined Vehicles