Optimizing IP Management for Chiplet-Based Designs

By Emily Yan

January 17, 2024

These chiplet-based designs are as complex as they are powerful. The complexity of managing massive IPs raises crucial questions: Can design teams effectively manage this intricacy via spreadsheets? What strategies are necessary to track and search extensive IPs? And importantly, how do teams address the looming concerns of security and compliance in this new era?

Keysight's acquisition of Cliosoft in 2023 marked a significant step towards empowering our global customers to tackle these challenges head-on. Our webinar on Feb 7 will offer an in-depth discussion about advanced methods for searching, reusing, and securing multiple silicon IPs. Can't wait until then? Get a head start with this blog on the essentials of chiplet and IP management.

Chiplet vs. Chip: What’s the difference

A traditional chip or monolithic SoC (system on chip) is a single integrated circuit where all components are built on the same silicon die. Following the Moore's Law, the number of transistors in a chip doubled about every two years. However, as the process technologies advance, particularly with smaller nodes (like 5 or 3 nm), the costs escalate substantially. Gordon Moore, in his 1965 paper, foresaw the end to his Law and the potential need to build large systems from smaller, interconnected functions.

“It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. The availability of large functions, combined with functional design and construction, should allow the manufacturer of large systems to design and construct a considerable variety of equipment both rapidly and economically.”

In contrast to traditional chips, chiplets are small, modular chips that, when connected, form a complete SoC. They can be likened to high-tech versions of Lego blocks. This approach offers numerous advantages, including enhanced performance, reduced power consumption, greater design flexibility, and cost savings. For instance, when designing a 10X10 mm chip in 3nm technology, cutting it up into four or five chiplets, most of them in a previous process node – the cost is way lower than its monolithic equivalent. This essentially means engineers can design complex chips more cost effectively and reuse IPs across different process nodes.

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