How to Make Chiplets a Viable Market

By Paul McLellan, Cadence

February 8, 2023

At the recent Chiplet Summit, there was a panel session on the last afternoon titled How to Make Chiplets a Viable Market. The panel was moderated by Meta's Ravi Agarwal, and the panelists were (from left to right in the photo):

• Travis Lanier of Ventana Micro Systems...actually Travis couldn't make it and Ventana was represented by Charles, but I didn't catch his last name
• Clint Walker of Alphawave Semi (fka Alphawave IP)
• Mark Kuemerle of Marvell
• Durgesh Srivastava of NVIDIA
• Kevin Yee of Samsung Foundry

Unusually, for a panel session, the room was completely full with lots of people standing at the back.

I think that this is one of the most interesting topics in the whole chiplet arena. I have no doubt that technical problems like chiplet die-to-die interfaces, creating good chiplet library formats, or improving testing for known-good-die will all be solved in time. But just what the chiplet business models will be remains foggy, to say the least. I've said before that the dream is to take an Intel CPU chiplet, an NVIDIA GPU chiplet, a Qualcomm modem chiplet, and an AMD/Xilinx FPGA chiplet, and put them all into the same system-in-package. We are a long way from that today!

The format was that each panelist spent a couple of minutes introducing themselves and showing a couple of slides. Then Ravi put up a slide with a few questions he'd already prepared. And then it was the audience's turn to ask questions of the panel.

I'll give my usual preamble to when I report on a panel. This is not verbatim what everyone said, it is me paraphrasing it. I put Q in front of each question to make them stand out. That means it is Ravi asking, or someone in the audience in the last section. I identify answers by the name of the company, so you don't have to remember who works for which company. Any remarks in square brackets are mine [and not something any of the panelists said].