Chiplets Open Pandora’s Box

By Daniel Nenni

February 1, 2024

Chiplets have simplified one area of design but opened pandora’s box on another front. The simulation complexity of each chiplet is lower but now the chiplet-to-chiplet interconnect has become complex. Folks are experimenting with different interconnect protocols, variations of UCIe, modifying UCIe settings, interface speeds, number of physical layers and so one. Now add legacy standards like AXI, new protocols like PICe6.0 and cache coherency to the mix.

All-in-all, this creates a completely new set of experiments. One for which the traditional emulation and RTL modelling will not work. You need first spend an effort on architecture trade-off, not just in selecting components. This will mean that you will have to conduct traffic analysis, application partitioning, system sizing and impact of different types of physical layer. Also, depending on the application the benchmark will be very different.

The UCIe specification is new and there are no clear benchmarks. Also, the UCIe specification only provides guidance on latency and power. Both are stringent requirements. This means that a Power-Performance-Area study is evitable. As you have protocol-protocol-protocol conversion such as PCIe 6.0 to UCIe to AXI, the modelling setup is complex.