Ncore Multi-Die Interconnect IP

Solve multi-core design challenges with safety support

Ncore Multi-Die is a configurable cache‑coherent interconnect with optional last‑level caches that supports full CPU cache coherency and I/O coherency for high‑performance system designs.

Ncore Multi‑Die extends the Ncore coherent interconnect across multiple chiplets, enabling scalable, high‑performance architectures that overcome reticle limits and, yield challenges, and addresses the growing requirement for modular compute and silicon process specialization in AI, automotive, HPC, and data‑centric SoCs.

Advantages: Create high-performance coherent SoCs

Scale Performance with Multi-Die Coherency

By extending Ncore coherency across up to four dies, designers can scale performance linearly through homogeneous replication or mix heterogeneous compute resources using the best process technology for each domain. Coherency remains transparent to software, preserving standard programming models.

Increase Bandwidth and Reduce Latency

With over 64 GB/s usable data bandwidth per link, and 256 GB/s per die, Ncore Multi‑Die provides the bandwidth needed for AI/ML and HPC workloads. Interleaving and link aggregation boost point‑to-point throughput, while message forwarding in the GIU minimizes latency.

Tune Systems for Flexibility and Design Requirements

Support for mesh and fully connected homogeneous or heterogeneous chiplet interconnect topologies allows designers to tailor the system for performance, cost, or physical layout constraints. Logical‑to‑physical remapping enables die rotation or mirroring while maintaining correct routing, easing interposer design.