Corsair: An In-memory Computing Chiplet Architecture for Inference-time Compute Acceleration
By Satyam Srivastava; Akhil Arunkumar; Nithesh Kurella; Amrit Panda; Gaurav Jain; Purushotham Kamath
d-Matrix Corporation
Abstract:
Advances in Generative AI (GenAI) have reinvigorated research into novel computing architectures such as Transformer. Transformer, characterized by low arithmetic intensity during most of the inference time, has become the cornerstone of GenAI underlying Large Language (LLM) and Reasoning Models (RM). Numerous solutions to the intense memory bandwidth problem have been proposed. Corsair is an architecture that targets this need using chiplet design, digital in-memory computing-based matrix engine, efficient die-to-die interconnects, block floating point numerics, and large high-bandwidth on-chip memories. We describe the Corsair chiplet, scaling approaches to compose larger systems, and outline the software stack. We formulate the inference-time requirements of LLM and RM computation, memory bandwidth, memory capacity, and interconnect efficiency for scaling. We also show how Corsair design perfectly fits these workloads. We present benchmark results from Corsair silicon that correlate strongly with the design and preview an estimate of workload-level improvements expected with Corsair.
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Technical Papers
- PICNIC: Silicon Photonic Interconnected Chiplets with Computational Network and In-memory Computing for LLM Inference Acceleration
- Hemlet: A Heterogeneous Compute-in-Memory Chiplet Architecture for Vision Transformers with Group-Level Parallelism
- CLIPGen: A Chiplet Link IP Modeling and Generation Framework for 2.5D Architecture Exploration
- CarbonPATH: Carbon-aware pathfinding and architecture optimization for chiplet-based AI systems
Latest Technical Papers
- Transient Multiscale Workflow for Thermal Analysis of 3DHI Chip Stack
- Dispersion-Engineered Terahertz Silicon Interconnects Enabling Terabit-Scale Data Links
- Design-Oriented Modeling of TSV Substrate Noise Coupling to Ring VCOs
- CLIPGen: A Chiplet Link IP Modeling and Generation Framework for 2.5D Architecture Exploration
- Wafer Warpage of Silicon Interposer in Manufacturing Processes for High Density 2.5D Advanced Packaging: Causes, Measurement, Analysis and Optimization