Chiplet design basics for engineers
By Andy Nightingale, Arteris | July 28, 2025
The world is experiencing an insatiable and rapidly growing demand for artificial intelligence (AI) and high-performance computing (HPC) applications. Breakthroughs in machine learning, data analytics, and the need for faster processing across all industries fuel this surge.
Application-specific integrated circuits (ASICs), typically implemented as system-on-chip (SoC) devices, are central to today’s AI and HPC solutions. However, traditional implementation technologies can no longer meet the escalating requirements for computation and data movement in next-generation systems.
From chips to chiplets
Traditionally, SoCs have been implemented as a single, large monolithic silicon die presented in an individual package. However, multiple issues manifest as designers push existing technologies to their limits. As a result, system houses are increasingly adopting chiplet-based solutions. This approach implements the design as a collection of smaller silicon dies, known as chiplets, which are connected and integrated into a single package to form a multi-die system.
For example, Nvidia’s GPU Technology Conference (GTC) has grown into one of the world’s most influential events for AI and accelerated computing. Held annually, GTC brings together a global audience to explore breakthroughs in AI, robotics, data science, healthcare, autonomous vehicles, and the metaverse.
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Technical Papers
- RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures
- ATSim: A Fast and Accurate Simulation Framework for 2.5D/3D Chiplet Thermal Design Optimization
- Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models
- A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models
Latest Technical Papers
- Monolithically Integrated Optical Through-Silicon Waveguides for 3D Chip-to-Chip Photonic Interconnects
- Mozart: A Chiplet Ecosystem-Accelerator Codesign Framework for Composable Bespoke Application Specific Integrated Circuits
- On-Package Memory with Universal Chiplet Interconnect Express (UCIe): A Low Power, High Bandwidth, Low Latency and Low Cost Approach
- 3D Electronic-Photonic Heterogenous Interconnect Platforms Enabling Energy-Efficient Scalable Architectures For Future HPC Systems
- Leveraging Modularity of Chiplets to Form a 4×4 Automotive FMCW-Radar in an eWLB-Package