Universal Chiplet Interconnect Express: An Open Industry Standard for Memory and Storage Applications

By Debendra Das Sharma (CXL Board Technical Task Force, Intel), Thomas Coughlin (Coughlin Associates)

Abstract

Continuing advances in computing will require chiplets connected by the Universal Chiplet Interconnect Express (UCIe) to create cost-effective high-performance customized applications and new memory hierarchies. The optical UCIe can expand this functionality to the pod and rack level.

There are many drivers for on-package integration of chiplets. Overcoming reticle limitations to deliver performance, functionality, and yield tradeoffs with larger dies is a primary reason why today volume CPUs and GPUs use chiplet-based solutions with proprietary scale-up interconnects. Chiplet approaches reduce the compromises required with monolithic designs. Lowering the overall portfolio cost with a time-to-market advantage is another motivation for deploying chiplets.

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