3DIO IP For Multi-Die Integration
Accelerate the scaling of system functionality with 3D packaging.
By Lakshmi Jain and Wei-Yu Ma (Synopsys)
October 17th, 2024 - SemiEngineering
The demand for high performance computing, next-gen servers, and AI accelerators is growing rapidly, increasing the need for faster data processing with expanding workloads. This rising complexity presents two significant challenges: manufacturability and cost. From a manufacturing standpoint, these processing engines are nearing the maximum size that lithography machines can etch on a reticle. As die sizes increase and yields decrease, the cost per die can rise substantially.
Gordon Moore once said, “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.” To meet the demands for higher performance, the chip design industry is shifting from system-on-chip (SoC) to system-in-package (SiP) through wafer-level packaging.
A heterogeneous SoC entails partitioning the SoC at the IO or core level, using a modular approach with different building blocks. This offers several advantages, including supporting SoCs that are growing beyond reticle size, improving die yield, and enabling design modularity. However, a heterogeneous die introduces new challenges which include increased design complexity due to close interaction between the dies and package, supporting testability across assembly and manufacturing processes, and thermal management due to the proximity of the dies. 3D integration enables heterogeneous integration of IC chips fabricated with different technologies and materials, and thus permits the realization of integrated, sophisticated, and multifunctional microsystems that have high performance, low cost, and compact size requirements.
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