Multi-Die Design Pushes Complexity To The Max
Continued scaling using advanced packaging will require changes across the entire semiconductor ecosystem.
By Ann Mutschler, Semiengineering (April 29, 2024)
Multi-die/multi-chiplet design has thrown a wrench into the ability to manage design complexity, driving up costs per transistor, straining market windows, and sending the entire chip industry scrambling for new tools and methodologies.
For multiple decades, the entire semiconductor design ecosystem — from EDA and IP providers to foundries and equipment makers — has evolved with the assumption that more functionality can be added into chips and packages, while improving the power, performance, and area/cost equation. But as the ability to pack all of this functionality into a single die or package becomes more difficult, the complexity of developing these devices has skyrocketed.
To read the full article, click here
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- Synopsys and Samsung Foundry Deepen Collaboration to Accelerate Multi-Die System Design for Advanced Samsung Processes
- Synopsys and TSMC Pave the Path for Trillion-Transistor AI and Multi-Die Chip Design
- Multi-Die Design Complicates Data Management
- Synopsys Powers World’s Fastest UCIe-Based Multi-Die Designs with New IP Operating at 40 Gbps
Latest News
- Siemens expands OSAT Alliance membership to build domestic semiconductor supply chains
- Marvell Delivers Advanced Packaging Platform for Custom AI Accelerators
- Executive Outlook: Chiplets, 3D-ICs, and AI
- AMD Acquires Enosemi to Accelerate Co-Packaged Optics Innovation for AI Systems
- ASE Announces FOCoS-Bridge With TSV; Latest Package Technology Reduces Power Loss by 3x for Next-Generation AI and HPC Applications