Broadcom Bets on 3.5D Packaging Technology to Build Bigger AI Chips

The tech integrates 2.5D packaging technology and 3D silicon stacking to usher in the next generation of “superchips” for AI.

James Morra, Electronic Design (January 16, 2025)

The semiconductor companies and startups on the front lines of the AI chip market are competing over scale as much as anything else. They’re all racing to roll out giant graphics processing units (GPUs) and other AI chips to handle the types of large language models (LLMs) at the heart of OpenAI’s ChatGPT and other state-of-the-art algorithms, which are becoming more computationally intense and power-hungry to train and run.

The most advanced AI chips in data centers can no longer fit on one monolithic slab of silicon. Instead, they consist of chiplets lashed together with 2.5D or 3D advanced packaging that get everything to mimic one large chip as much as possible.

Broadcom is trying to build even bigger AI chips with its 3.5D packaging technology that was introduced last month. By stacking accelerator chips with 3D integration before placing them next to each other with 2.5D, the Extreme Dimension System in Package (XDSiP) platform can accommodate more than 6,000 mm² of silicon in a package. The company said it can put the 3D-stacked accelerators and other chiplets on a silicon interposer before surrounding them with up to 12 high rises of high-bandwidth memory (HBM).

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