A sneak peek at chiplet standards
By Majeed Ahmad, EDN (September 4, 2023)
The scaling of system-on-chip (SoC) architectures is hitting the wall, paving the way for die-to-die interconnect in heterogenous single-package systems commonly known as chiplets. But while these chiplet-optimized interconnect technologies are gaining significant traction, they are still in their infancy.
That makes chiplet interconnect standards crucial for the new multi-die semiconductors era. Below is a brief outline of three standards that are considered critical in the present evolution of chiplets. These standards will likely play a vital role in creating an open chiplet ecosystem.
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- Eliyan Showcases Next-Generation Chiplet Interconnect and Memory Innovations at OCP Global Summit 2025
- Alphawave Semi Showcases Advances in PCIe Over Optics and Chiplet Integration at SC25
- Tenstorrent Announces Open Chiplet Atlas™ Ecosystem to Accelerate and Standardize an Open Chiplet Ecosystem
- 400Gbps/800Gbps IOWN APN demonstration at OFC2024 by multi-vendor products leveraging photonics-electronics convergence device and open standards
Latest News
- Qualcomm Acquires Ventana Micro Systems, Deepening RISC-V CPU Expertise
- Imec mitigates thermal bottleneck in 3D HBM-on-GPU architectures using a system-technology co-optimization approach
- UMC Licenses imec’s iSiPP300 Technology to Extend Silicon Photonics Capabilities for Next-Generation Connectivity
- Geometry Challenges in Multidie Thermal Management
- SCHMID Announces Successful Delivery and Installation of its InfinityLine C+ System to a Leading Japanese Advanced Packaging Customer