Watching The Next Big Semiconductor Transition Unfold

By Frank Schirrmeister

February 15, 2024

Impressions from the 2nd Annual Chiplet Summit

From February 6th to 8th, 2024, a fascinating mix of engineers descended on the Santa Clara convention center for the Chiplet Summit. It felt like representatives from all aspects of the semiconductor ecosystem attended – providers of Semiconductor Intellectual Property (IP) like us, Electronic Design Automation (EDA) tool vendors, Wafer Fab Equipment (WFE) providers, Semiconductor Foundries, “Fabless” chip companies, and Integrated Design Manufacturers (IDMs) all in one place to discuss one thing – chiplets. The agenda varied from sessions discussing how to develop them, the architectures to integrate them, the substrates to assemble them on, the standards needed to connect them, the business models to enable them, and the industries and application domains setting requirements for them.

A bifurcated development landscape

The big takeaway was the not-so-subtle bifurcation of the development landscape, even though some of the panel discussions sometimes mixed and confused them.

On the one hand, chiplets are a reality and necessity today. Plenty of examples on the slides last week illustrated the designs of companies like AMD, Intel, NVIDIA, Apple, Google, Samsung, Meditek, Qualcomm, and HiSilicon. The main driver here is complexity. What developers used to integrate into one System-on-Chip (SoC) has reached the “reticle limits.” The complexity requirements exceed what fits onto one reticle, and yields decline when getting too close to the technology limits. I heard several references to a cost analysis that AMD did in 2021. The article “The Economics of Chiplets” offers an excellent summary. The key here is that the chiplets are essentially co-designed (with the exception, perhaps, of memory), and the companies mentioned above can control all design aspects, including, for instance, the Serdes technology at the chiplet boundaries, etc. It’s expensive to do that, and only a few markets offer the appropriate ROIs, and a few companies can afford the development NRE cost.

On the other hand – for everybody else who cannot afford to control all design aspects because they pay for them, there was a lot of discussion about an open ecosystem of chiplets. Instead of building an SoC with licensed IP blocks and added differentiation, can the design be integrated using reused chiplets? Are chiplets the next level of Semiconductor IP? An extreme example would be an SoC that was integrated monolithically in the past and is now wholly disaggregated into chiplets. One panelist called it, very fittingly, the “Legolization” of semiconductor design using chiplets. For this to work, many things need to fall in place. The industry needs to agree on standards for the PHY implementation between chiplets – UCIe, BoW, and XSR are in the running. The industry needs to agree on protocols for data transport between chiplets, considering networks-on-chips (NoCs). Amba AXI and CHI were very visible as candidates, and CXL also came up often. Most importantly, the industry must find business models and value propositions for chiplet-based designs outside the mega-big developments only a few companies can afford. That’s because the value mentioned above for massive designs (the AMD case) changes towards an IP-reuse type value in an “Open Chiplet Ecosystem” world.

We are looking at two fundamentally different paths here, with some technology overlap. Once established, UCIe or BoW-type standard interfaces can be helpful for both closed and open ecosystems.

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