Integrated Design Ecosystem™ for Chiplets and Heterogeneous Integration in Advanced Packaging Technology

By Dr. Lihong Cao, Sr. Director of Technology & Business Development

January 21, 2025

As the demand for high-performance computing (HPC) continues to grow, chiplets and heterogeneous integration have emerged as key solutions due to their significant advantages in improving yield, reusing IP, enhancing performance, and optimizing costs. The integration of chiplets, particularly for AI applications, necessitates a greater number of connections than traditional monolithic system-on-chip (SoC) designs. These connections must ensure high density, efficient data transfer, and effective power delivery. This has led to an increased demand for advanced packaging that features a higher number of interconnects and larger body sizes. The layout density of these packages can be tens to hundreds of times greater than that of conventional FCBGA packages. The high density and complex connectivity in advanced packaging introduce new challenges for packaging design and assembly manufacturing validation.

To address these challenges, ASE has developed the Integrated Design Ecosystem™ (IDE), a collaborative design toolset optimized to enhance advanced package architecture across its VIPack™ platform. The IDE facilitates a smooth transition from single-die SoCs to multi-die disaggregated IP blocks, including chiplets and memory, using 2.5D or advanced fan-out structures.

Package Design Challenges for Chiplets Integration

Traditionally, IC chip design and package layout design have been planned and executed separately for monolithic SoC with FCBGA package. However, as the transition from single monolithic SoCs to multi-chiplet architectures becomes inevitable, designers face increasing challenges in optimizing the interconnections between chiplets to enhance performance, making the design process significantly more complex. Furthermore, the die-to-die interconnects for chiplets integration are often proprietary links from various customers, which creates further design constraints and hinders the adoption of advanced packaging technologies.

For instance, as illustrated in the picture below, a standard FCBGA package for a monolithic die measures 62.5 x 62.5 mm² and has around 30,000 I/O pins. In contrast, when using chiplets — such as one ASIC die and one high-bandwidth memory (HBM) — a silicon interposer or redistribution layer (RDL) interposer is required to integrate the chiplets. While the size of the advanced package remains the same, the number of pins can increase fourfold to approximately 160,000.