How Cadence Is Expanding Innovation for 3D-IC Design
The market is trending towards integrating and stacking multiple chiplets into a single package to meet the growing demands of speed, connectivity, and intelligence. However, designing and signing off chiplets and packages individually is time-consuming and inefficient. In addition to planning, and aligning the chip stack, standard design closure checks like timing and power signoff, the system-level effects such as thermal and mechanical stress must be considered. This is where the comprehensive Cadence Integrity 3D-IC platform comes in, with its unique features designed to address these system-level challenges that may impact individual chip design closure.
Cadence is continuously expanding the innovation for 3D-IC design through research partnerships. During the recent CadenceLive Silicon Valley, CT Kao, Product Engineering Director at Cadence, presented how the Cadence Integrity 3D-IC platform and partnerships are paving the way for improvements in the next-gen multi-chiplet design solution. This blog is an excerpt from a presentation at CadenceLive Silicon Valley, 2024. If you missed the chance to watch this presentation live, register to watch this and other 3D-IC/Chiplet presentations on the CadenceLIVE on-demand site.
To read the full article, click here
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Blogs
- Using Voltus IC Power Integrity to Overcome 3D-IC Design Challenges
- Cadence Collaborates with TSMC to Shape the Future of 3D-IC
- Cadence Recognized for Accelerating AI and 3D-IC Applications by Samsung Foundry
- How to Make Chiplets a Viable Market
Latest Blogs
- AMI Outlines Full Support for Arm Total Design Chiplet Architecture to Custom Silicon Designers and Producers at APAC ATD Summit
- Faster, More Collaborative SoC and Chiplet Architecture Exploration: Introducing Synopsys Platform Architect Development Kit (PADK)
- Multi-Die Design Challenges: Industry Leaders Provide Insights and Guidance
- UCIe Full SI Analysis Flow with Compliance Check for Heterogeneous Integration
- Foundry 2.0 – the New Path Forward for Moore’s Law