How Cadence Is Expanding Innovation for 3D-IC Design

By Vinod Khera

June 12, 2024

The market is trending towards integrating and stacking multiple chiplets into a single package to meet the growing demands of speed, connectivity, and intelligence.  However, designing and signing off chiplets and packages individually is time-consuming and inefficient. In addition to planning, and aligning the chip stack, standard design closure checks like timing and power signoff, the system-level effects such as thermal and mechanical stress must be considered. This is where the comprehensive Cadence Integrity 3D-IC platform comes in, with its unique features designed to address these system-level challenges that may impact individual chip design closure.

Cadence is continuously expanding the innovation for 3D-IC design through research partnerships. During the recent CadenceLive Silicon Valley, CT Kao, Product Engineering Director at Cadence, presented how the Cadence Integrity 3D-IC platform and partnerships are paving the way for improvements in the next-gen multi-chiplet design solution. This blog is an excerpt from a presentation at CadenceLive Silicon Valley, 2024. If you missed the chance to watch this presentation live, register to watch this and other 3D-IC/Chiplet presentations on the CadenceLIVE on-demand site.

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