Revolutionizing High-Performance Silicon: Alphawave Semi and Arm Unite on Next-Gen Chiplets

Alphawave Semi's partnership with Arm marks a major advancement in enabling high-performance technologies for 6G/5G network infrastructure, cloud, and edge applications.

As 5G wireless communications systems continue to be deployed, enterprises are busy planning for 6G —the next generation of wireless communications set to transform our lives. Poised to merge communication and computing, 6G promises to create a hyperconnected world that blends digital and physical experiences with ultra-fast speeds and low latency as a starting point.

Building on the foundations laid by 5G, 6G will continue supporting improved data latency, security, reliability, and the ability to process massive volumes of data in real-time. It will also challenge what’s possible by bringing new, groundbreaking capabilities to the forefront, including expanded ubiquitous connectivity, integrated sensing and communication, and advanced artificial intelligence.
 
In today’s technology-driven era, we rely on our handhelds, smartphones, and mobile devices to fulfill day-to-day tasks, most of which are driven by on-device or cloud-based AI and ML. Connectivity and compute power are the most important factors enabling on-cloud large language models (LLMs) to process and respond to human interaction. The communication infrastructure currently operates over 5G networks. It started not long ago with bandwidth in the kilobits per second (Kbps) range in 2G and has now evolved to gigabits per second (Gbps) in 5G. On the horizon, the existing 5G wireless communication infrastructure will soon evolve to 6G, offering bandwidths of terabits per second (Tbps). A much higher network bandwidth is needed with the increasing number of devices and complex AI workloads. Network infrastructure giants are already looking to update their hardware to support speeds 50-100 times faster than 5G, with air latency under 100 microseconds, and even wider network coverage and reliability.

With this new infrastructure for 6G, carrier support and hardware/software support will require new RF designs and chipsets capable of supporting higher communication frequencies, possibly up to 1 THz. Although newer networks may be designed for more data bits per kilowatt of power efficiency, the increase in density, traffic, and processing speeds tends to negate these savings.

The wireless technology trend of the existing 5G network is built around innovation in processors and wireless technology on mobile devices, and in wireless base stations and cells. Base stations are replaced by RUs (radio units), DUs (distributed units), and CUs (centralized units). The radio units manage antennas in real-time through multicore processor chips. The distributed and centralized units provide support for the lower and upper layers of the protocol stack, respectively. These protocol stacks operate on compute chiplets, which are mounted on hardware acceleration cards to handle protocol processing. Radio, distributed, and centralized units need to handle a lot of radio processing and traffic data. With even higher throughput and extremely complex workloads in the new 6G infrastructure, network architecture, software, and hardware accelerator card equipment will need an upgrade or redesign to process and handle much larger amounts of data. The processor compute chiplets on the accelerator cards manage up to dozens of antennas simultaneously and will need to grow in compute power as requirements become more complex with the move to 6G.

To fulfill the needs of this rapidly advancing semiconductor industry, Alphawave Semi is collaborating with Arm on a sophisticated chiplet that uses Arm’s Neoverse Compute Subsystems (CSS). These compute chiplets are vital for supporting the demanding requirements of 6G/5G infrastructure, cloud and edge compute applications and for handling enterprise networking, server, and AI/ML markets. This partnership integrates the silicon-proven IP portfolio from Alphawave with Arm’s Neoverse CSS N3 to handle intensive workload efficiency, performance optimization and power savings in both compute and accelerator chiplets.

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