The Next Frontier in Semiconductor Innovation: Chiplets and the Rise of 3D-ICs

by Jayashankar Narayanankutty, Group Director, Cadence Design Systems

As we are ushered into a future brimming with digital complexity, it’s become exceedingly clear that the lifeblood of this new era is pumped by one crucial industry: semiconductors. From smartphones to servers underpinning the cloud, semiconductor chips are indispensable in our march toward an increasingly tech-dependent reality. One common thing in most devices around us is that the real estate available on them for specific workloads is getting smaller, and devices must run multiple workloads optimally. This can only be achieved by integrating as many functions as possible into a system-on-chip (SoC), making them smaller and more reliable. The industry has followed Moore’s law for decades to meet such demands by reducing transistor sizes. However, with artificial intelligence (AI) /machine language (ML) and high-performance computing (HPC), the demand for compute performance and data transfer for hyperscale data centers is at an all-time high. 

The chip manufacturers are facing technological and economic challenges at advanced nodes, and there has been a need to find innovative solutions and achieve performance improvements with reduced power. Stacking chips in the same package (3D) and a multi-chiplet system with a silicon interposer on the same package (2.5D) are emerging as solutions. By using advanced interconnect technology to combine hardened IP blocks or specialized chiplets, engineers can avoid the compounding issues of extreme transistor shrinkage, such as increased defect rates and overheating.

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