Advanced Packaging and Chiplets Can Be for Everyone
By Boris Chau, Project Leader, Faraday Technology Corporation
EETimes (November 29, 2024)
The chiplet revolution is upon us. What began in laboratories as multi-die science projects has eventually evolved. A giant company like AMD, Intel or Nvidia can produce—either at TSMC or, in Intel’s case, internally—a giant, startlingly expensive CPU or GPU multi-die assembly using advanced packaging to achieve remarkable density, power efficiency and performance.
However, the real promise of chiplets is something different: to democratize the design of complex silicon systems so that even systems developers and small-fabless semiconductor companies could develop them.
Today, there are both promising signs and notable obstacles to this vision. But I believe it is already possible for a modest design team to achieve a chiplet-based design today. However, that requires a good understanding of the variables involved and how to manage these in delivering the final design. Very likely today, this will involve using an external partner with that expertise.
This advance cannot come too soon. As the package becomes a critical factor in system performance, integrating multiple semiconductor dies—often designed and manufactured by different companies—within the same package will be essential.
To read the full article, click here
Related Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
Related Technical Papers
- Wafer Warpage of Silicon Interposer in Manufacturing Processes for High Density 2.5D Advanced Packaging: Causes, Measurement, Analysis and Optimization
- Generative Design of Liquid-Cooling Channels for Thermal Management of 2.5D and 3D Integrated Advanced Packaging
- Predicting Cure Evolution and Thermal Endurance of a Highly Filled Epoxy Underfill for Advanced Packaging
- Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond
Latest Technical Papers
- Cu-Cu Hybrid Bonding for Chiplets Heterogeneous Integration
- Location-Aware Caching Mechanism for minimizing performance degradation induced by inefficient inter-chiplet data path
- Predicting Cure Evolution and Thermal Endurance of a Highly Filled Epoxy Underfill for Advanced Packaging
- A Unified Interconnection Network for Chiplet-Based Scaling of the BrainScaleS Neuromorphic System
- Fengshui: Demystifying Chiplet Ecosystem and Bespoke Neural Network Accelerator Codesign