TSMC looks to standardise chiplet protocols in "world changing" move
By Nick Flaherty, eeNews Europe (October 9, 2023)
TSMC is looking to develop a standard data format for chiplet designs that would be used by all the EDA design tool and assembly and test providers.
This is part of a move to the 3D Blox technology for building chiplet designs on the TSMC CoWoS process. The aim is to provide common data for chiplets from different silicon suppliers, substrate and PCB makers and the OSAT assembly and test companies.
“Today most of the chips except for the memories come from TSMC but the goal is to mix and match but that is still some way to go but we are trying to get there,” said Dan Kochpatcharin, head of Design Infrastructure at TSMC.
To read the full article, click here
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- Socionext Announces Collaboration with Arm and TSMC on 2nm Multi-Core Leading CPU Chiplet Development
- Chiplet Pioneer Eliyan Achieves First Silicon in Record Time with Implementation in TSMC 5nm Process, Confirms Most Efficient Chiplet Interconnect Solution in the Multi-Die Era
- Chiplet Pioneer Eliyan Joins UCIe and JEDEC Industry Standardization Organizations, Expands Veteran Leadership Team to Accelerate Adoption of Breakthrough Die-to-Die Interconnect Solution
- TSMC Announces Breakthrough Set to Redefine the Future of 3D IC
Latest News
- Silicon Box Celebrates Fourth Anniversary with Rapid Growth, New Milestones
- Novel Assembly Approaches For 3D Device Stacks
- Resonac and PulseForge Unite to Advance Photonic Debonding for Next-Gen Semiconductor Packaging
- Arm: Chiplets Can’t Deliver on TCO Without an Ecosystem
- Distributing Intelligence Inside Multi-Die Assemblies