How can in-package optical interconnects enhance chiplet generative AI performance?

By Jeff Shepard, Microcontroller Tips (March 1, 2024)

Generative artificial intelligence (AI) requires rapid and continuous movement of large amounts of data. In a growing number of instances, electrical input/output (I/O) connections between the ICs in chiplets are becoming a bottleneck to higher performance. Key electrical I/O performance barriers include power efficiency, bandwidth, and latency. This FAQ looks at the anticipated benefits of using in-package optical I/O (IOI) in place of today’s electrical I/O in chiplets and closes with a look at emerging IOI solutions and technologies.

IOI solutions represent the latest in a long line of advancements in optical interconnects, beginning with pluggable optical transceivers replacing or supplementing electrical I/Os in data centers (Figure 1). For example, electrical Serializer/Deserializer (SerDes) is a common form of high-speed connectivity. It consists of a pair of blocks that convert data between serial data and parallel interfaces in each direction. However, exceeding 112 gigabits per second (Gbps) is extremely challenging because the large signal losses in copper interconnects make it hard to transmit data further than a few centimeters. The replacement of SerDes with OIO in chiplets is expected to eliminate electrical I/O bottlenecks and dramatically increase data transmission speeds. Critical barriers to increasing I/O performance include power efficiency, latency, and bandwidth density and reach.

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