Chiplets: Piecing Together the Next Generation of Chips (Part I)
By Eric Beyne, Geert Van der Plas (imec)
This is the first part of a two-part series dedicated to chiplets. The series addresses recent developments in interconnect technologies (part I) and testing strategies and standardization efforts (part II).
Chiplets, beyond the hype
Ranked by MIT Tech Review as one of ten breakthrough technologies of 2024, chiplets have made quite the entrance into the semiconductor world. Chiplets are small, modular chips serving a specific function, such as CPUs or GPUs that can be mixed and matched into a complete system. The Lego-like approach hands manufacturers the flexibility to compose a system cost-effectively with lower entry costs for new chip designs and increased efficiency and performance. One way chiplets achieve optimization is by tailoring technology strategically. For example, IO and bus chiplets use reliable legacy nodes, while compute chiplets employ cutting-edge technology for peak performance. Memory chiplets embrace emerging memory technologies, ensuring adaptability to diverse semiconductor demands. Additionally, chiplet-based designs accelerate the development process because outdated chiplets can easily and more frequently be updated. Finally, chiplets typically boast high yield rates because they are often smaller with simpler designs, they start with known good dies after pre-bond testing and they can rely on repair strategies for defective interconnects.
Fragmenting large monolithic system-on-chips
Chiplet-based designs answer the slowing down of Moore’s Law that has fueled the semiconductor industry for the past decades. To ensure the biannual doubling of components on integrated circuits, chipmakers explored ways to make transistors smaller and cram more onto chips, resulting in sizeable monolithic system-on-chip (SoC) designs. Mobile phones are a testament to the success of monolithic designs, combining mathematical functions, display, wireless communication, audio, etc., all into one single 100mm2 chip. However, further scaling grew tremendously expensive for a minimal performance advantage. Hence, the idea is to divide the large, complex SoC into smaller chiplets and link them together to build a system for specific applications.
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