Axelera plans AI chiplets for automotive
By Nick Flaherty, eeNews Automotive (January 10, 2024)
Dutch edge AI chip designer Axelera is planning a version of its in memory computing AI architecture for automotive chiplets.
“We are already part of the imec chiplet consortium and a EU consortium to standardise RISC-V in AI acceleration,” said Fabrizio del Maffeo, CEO and co-funder of Axelera AI in the Netherlands tells eeNews Europe Automotive.
Belgian research lab imec pulled together a group to develop chiplet technology for automotive that includes European car makers.
Related Chiplet
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
- UCIe based 12-bit 12-Gsps Transceiver
Related News
- ASE’s VIPack™ Enables Innovational AI Devices Through Advanced Interconnect Technology for Chiplets
- Automotive AI: ADAS, Functional Safety and Chiplets
- TSMC plans automotive chiplet process for 2025
- TSMC to Provide 3DIC Integration for AI Chips in 2027, Featuring 12 HBM4 and Chiplets Manufactured with A16
Latest News
- Alphawave Semi Partners with PCISig, CXL Consortium, UCIe Consortium, Samtec and Lessengers to Showcase Advances in AI Connectivity at Supercomputing 2024
- Lightmatter and Amkor Technology Partner to Build World’s Largest 3D Photonics Package
- Lightmatter and ASE Partner to Bring 3D Photonics to Market
- Breaking Boundaries: Chiplet Interconnects, SDVs & electronica 2024
- The Evolution of Interconnects in Microelectronics Packaging