HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement

By Patrick Iff ^∗, Maciej Besta ^∗, Matheus Cavalcante ^†, Tim Fischer ^†, Luca Benini ^†‡ and Torsten Hoefler ^∗
∗ Department of Computer Science, ETH Zurich, Zurich, Switzerland
^† Department of Information Technology and Electrical Engineering, ETH Zurich, Zurich, Switzerland
^‡ Dept. of Electrical, Electronic and Information Engineering, University of Bologna, Italy

Abstract

2.5D integration is an important technique to tackle the growing cost of manufacturing chips in advanced technology nodes. This poses the challenge of providing high-performance inter-chiplet interconnects (ICIs). As the number of chiplets grows to tens or hundreds, it becomes infeasible to hand-optimize their arrangement in a way that maximizes the ICI performance. In this paper, we propose HexaMesh, an arrangement of chiplets that outperforms a grid arrangement both in theory (network diameter reduced by 42%; bisection bandwidth improved by 130%) and in practice (latency reduced by 19%; throughput improved by 34%). HexaMesh enables large-scale chiplet designs with high-performance ICIs.

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