How 3D-IC Will Change Chip Design
Stacking dies will dramatically improve performance, but it’s still a work in progress.
By Ed Sperling, Semi Engineering | October 8, 2025
Semiconductor Engineering sat down to discuss 3D-IC design challenges and the impact on stacked die on EDA tools and methodologies, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence‘s Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities business manager at Keysight Technologies, and Amlendu Shekhar Choubey, senior director of product management for Synopsys‘ 3D-IC compiler platform.
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