Floor-Planning Evolves Into The Chiplet Era

Automatically mitigating thermal issues becomes a top priority in heterogeneous designs.

By Karen Heyman, Semiengineering (July 25, 2024)

3D-ICs and heterogeneous chiplets will require significant changes in physical layout tools, where the placement of chiplets and routing of signals can have a big impact on overall system performance and reliability.

EDA vendors are well aware of the issues and working on solutions. Top on the list of challenges for 3D-ICs is thermal dissipation. Logic typically generates the most heat, and stacking logic chiplets on top of other logic chiplets requires a way to dissipate that heat. In a planar SoC, this is typically handled through a heat sink or the substrate. But in a 3D-IC, the substrate needs to be thinned out to minimize the distance that signals must travel, which reduces the substrate’s ability to transfer heat. In addition, heat can become trapped between chiplets, so a heat sink is no longer an option. The way around this is to carefully configure different layers so that heat is spread out across the chip, or confined to an area where it can be effectively removed, and this needs to be built into the automation tools.

“The transition to a chiplet design paradigm will impact modern place-and-route design flows, requiring an optimization of logical partitions among chiplets,” said Tony Chan Carusone, chief technology officer at Alphawave Semi. “This means the place-and-route design flow for chiplet-based systems must consider multi-die integration, the potential for heterogeneous technologies, and manage the complexity of high-density die-to-die interconnects. This will require awareness of the possibilities and constraints offered by different fabrication and packaging technologies.”

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