Eliyan Applauds Release of OCP’s Latest Multi-die Open Interconnect Standard, BoW 2.0; Demonstrates Industry’s First Working Silicon Compliant with the Spec
SANTA CLARA, Calif. – August 16, 2023 – Eliyan Corporation, credited for the invention of the semiconductor industry’s highest-performance and most efficient chiplet interconnect, announced its support for and compatibility with BoW 2.0, the new latest specification for a die-to-die interconnect standard from the Open Compute Project (OCP). Eliyan’s team has deep roots in driving standards-based technologies to solve important industry challenges, which includes earlier work with OCP and its Open Domain Specific Architecture (OSDA) to propose BoW (Bunch of Wires) interconnect approach as a basis for the organization’s multi-die interconnect specification.
“We support the evolution of BoW in this latest version, which notably doubles the data rate per lane from 16Gbps to 32Gbps, and provides support for configurable directionality, both of which we support in our silicon-proven solution. As a foundational contributor to this effort, and the first company to demonstrate compliance with the latest specification in a working chip, we are excited about the potential for the BoW die-to-die interconnect method to advance the capabilities of high-performance computing and memory efficiency in key applications such as Generative AI,” said Ramin Fajadrad, founder and CEO of Eliyan.
Farjadrad is an inventor of the original interconnect technology behind BoW, which he proposed to OCP in 2018 and it was used as the basis for the development of the initial specification of the standard. Eliyan specifically developed the BoW on standard packaging to address the need for highly efficient die-to-die PHYs to connect large number of chiplets with different functions in one package, which is critical for realizing the scale of performance and integration required by compute-intensive applications in data centers, cloud computing, and, most importantly, artificial intelligence. Farjadrad’s experience also includes pioneering work in creating connectivity technologies such as PAM4 SerDes, Multi-Gbps Enterprise Ethernet, and Multi-Gbps automotive Ethernet that were eventually adopted as IEEE standards.
“Eliyan has demonstrated a commitment to addressing the critical challenges the high-performance computing industry faces as it applies next generation architectures and to the evolving needs of OCP members in cloud computing, data centers, edge computing and AI processing. We welcome their development efforts to demonstrate 5nm silicon proof of a PHY compliant with the BoW 2.0 specification for chiplet connectivity and look forward to their continued contributions to the Open Chiplet Economy,” said Bapi Vinnakota, OSDA Lead at OCP.
Eliyan’s recently demonstrated the industry’s first working silicon that is compliant with BoW 2.0 specification, and surpasses the standard’s stated performance scope, with its NuLink PHY, implemented in a 5nm standard foundry process, requiring no advanced packaging techniques such as silicon interposers. The chip operates at 40Gbps/bump delivering over 2.2Tbps/mm of beachfront bandwidth at 130um pitch on standard organic packaging while meeting aggressive power and area targets. The highly area efficient NuLink™ PHY is bump limited and can deliver up to 3Tbps/mm once implemented on available standard packaging technologies at finer bump pitches, leveraging its innovative interference cancellation techniques.
About The Open Compute Project
The Open Compute Project Foundation (OCP) was initiated by Facebook in 2011 with a mission to apply the benefits of open source and open collaboration to hardware and rapidly increase the pace of innovation in, near and around the data center’s networking equipment, general purpose and GPU servers, storage devices and appliances, and scalable rack designs. OCP’s collaboration model is being applied beyond the data center, helping to advance the telecom industry & EDGE infrastructure.
About Eliyan
Eliyan Corporation is leading the chiplet revolution, focusing on a fundamental challenge with scaling semiconductor performance, size, power, and cost to meet the needs of high-performance computing applications, from desktop to datacenter. It has developed a breakthrough method to enable the industry’s highest performing interconnect for homogenous and heterogenous multi-die architectures using standard packaging substrates, enabling increased sustainability through reduction in costs, manufacturing waste and power consumption. The company’s Bunch of Wires (BoW) technique, invented by founder Ramin Farjadrad and proven to increase performance by 2x and reduce power in half in advanced process technologies, provides a more efficient approach to developing chiplet-based architectures – which are the pathway to the continued scaling of Moore’s Law. More information can be found here. www.eliyan.com
Related Chiplet
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
- UCIe based 12-bit 12-Gsps Transceiver
Related News
- Eliyan Supports Latest Version of UCIe Chiplet Interconnect Standard, Continues to Drive Performance and Bandwidth Capabilities to 40Gbps and Beyond to Help Meet the Needs of the Multi-die Era
- Chiplet Pioneer Eliyan Achieves First Silicon in Record Time with Implementation in TSMC 5nm Process, Confirms Most Efficient Chiplet Interconnect Solution in the Multi-Die Era
- Chiplet Pioneer Eliyan Joins UCIe and JEDEC Industry Standardization Organizations, Expands Veteran Leadership Team to Accelerate Adoption of Breakthrough Die-to-Die Interconnect Solution
- Cadence Expands Support for 3Dblox 2.0 Standard with New System Prototyping Flows
Latest News
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- Silicon Box welcomes European Commission approval of €1.3 billion Italian State aid measure to support new advanced packaging facility in Novara
- Fraunhofer IMS Takes a Key Role in Establishing the APECS Pilot Line
- EdgeCortix Joins AI-RAN Alliance to Accelerate the Integration of AI and Next-gen RAN Infrastructure
- Cadence Rolls Out System Chiplet to Reorganize the SoC